1. Data Flow Modeling of Combinational Logic
ECE 545
Lecture 5
Data Flow Modeling of Combinational Logic

2. Required reading P. Chu, RTL Hardware Design using VHDL
Chapter 4, Concurrent Signal Assignment
Statements of VHDL

3. Dataflow VHDL Design Style
ECE 448 – FPGA and ASIC Design with VHDL

4. behavioral (sequential)
VHDL Design Styles
VHDL Design
Styles
Testbenches
dataflow
behavioral (sequential)
structural
Concurrent
statements
Components and
interconnects
Sequential statements
Registers
State machines
Instruction decoders
Subset most suitable for synthesis

5. Synthesizable VHDL Dataflow VHDL Design Style VHDL code synthesizable

6. Register Transfer Level (RTL) Design Description
Today’s Topic
Combinational
Logic
Combinational
Logic …
Registers

7. Data-Flow VHDL
Concurrent Statements
concurrent signal assignment ()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)
generate scheme for equations
(for-generate)

8. Data-flow VHDL
Major instructions
Concurrent statements
concurrent signal assignment ()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)
generate scheme for equations
(for-generate)

9. Data-flow VHDL: Exampley s
cin
cout

10. Data-flow VHDL: Example (1)
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
PORT ( x : IN STD_LOGIC ;
y : IN STD_LOGIC ;
cin : IN STD_LOGIC ;
s : OUT STD_LOGIC ;
cout : OUT STD_LOGIC ) ;
END fulladd ;

11. Data-flow VHDL: Example (2)
ARCHITECTURE dataflow OF fulladd IS
BEGIN
s <= x XOR y XOR cin ;
cout <= (x AND y) OR (cin AND x) OR (cin AND y) ;
END dataflow ;

12. Logic Operators Logic operators Logic operators precedence
and or nand nor xor not xnor
only in VHDL-93
or later
Highest
No order precedents
not
and or nand nor xor xnor
Lowest

13. No Implied Precedence Wanted: y = ab + cd Incorrect
y <= a and b or c and d ;
equivalent to
y <= ((a and b) or c) and d ;
y = (ab + c)d
Correct
y <= (a and b) or (c and d) ;
No order precedents

14. Implementation of last statement
E.g.,
status <= '1';
even <= (p1 and p2) or (p3 and p4);
arith_out <= a + b + c - 1;
Implementation of last statement
RTL Hardware Design
Chapter 4

15. Signal assignment statement with a closed feedback loop
a signal appears in both sides of a concurrent assignment statement
E.g., q <= ((not q) and (not en)) or (d and en);
Syntactically correct
Form a closed feedback loop
Should be avoided
RTL Hardware Design
Chapter 4

16. Data-flow VHDL
Major instructions
Concurrent statements
concurrent signal assignment ()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)
generate scheme for equations
(for-generate)

17. Conditional concurrent signal assignment
When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;

18. Most often implied structure
When - Else
target_signal <= value1 when condition1 else
value2 when condition2 else
. . .
valueN-1 when conditionN-1 else
valueN;
Value N
Value N-1
Condition N-1
Condition 2
Condition 1
Value 2
Value 1
Target Signal … 1 .… 1 1

19. 2-to-1 “abstract” mux sel has a data type of boolean
If sel is true, the input from “T” port is connected to output.
If sel is false, the input from “F” port is connected to output.
RTL Hardware Design
Chapter 4

20. RTL Hardware Design
Chapter 4

21. RTL Hardware Design
Chapter 4

22. RTL Hardware Design
Chapter 4

23. E.g.,
RTL Hardware Design
Chapter 4

24. E.g.,
RTL Hardware Design
Chapter 4

25. RTL Hardware Design
Chapter 4

26. E.g.,
RTL Hardware Design
Chapter 4

27. Signed and Unsigned Types
Behave exactly like
STD_LOGIC_VECTOR
plus, they determine whether a given vector
should be treated as a signed or unsigned number.
Require
USE ieee.numeric_std.all;

28. Operators Relational operators
Logic and relational operators precedence
= /= < <= > >=
Highest
not
= /= < <= > >=
and or nand nor xor xnor
No order precedents
Lowest

29. Priority of logic and relational operators
compare a = bc
Incorrect
… when a = b and c else …
equivalent to
… when (a = b) and c else …
Correct
… when a = (b and c) else …
No order precedents

30. VHDL operators

31. Data-flow VHDL
Major instructions
Concurrent statements
concurrent signal assignment ()
conditional concurrent signal assignment
(when-else)
selected concurrent signal assignment
(with-select-when)
generate scheme for equations
(for-generate)

32. Selected concurrent signal assignment
With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;

33. Most Often Implied Structure
With –Select-When
with choice_expression select
target_signal <= expression1 when choices_1,
expression2 when choices_2,
. . .
expressionN when choices_N;
expression1
choices_1
expression2
choices_2
target_signal
expressionN
choices_N
choice expression

34. Allowed formats of choices_k
WHEN value
WHEN value_1 | value_2 | .... | value N
WHEN OTHERS

35. Allowed formats of choice_k - example
WITH sel SELECT
y <= a WHEN "000",
c WHEN "001" | "111",
d WHEN OTHERS;

36. Syntax Simplified syntax: with select_expression select
signal_name <=
value_expr_1 when choice_1,
value_expr_2 when choice_2,
value_expr_3 when choice_3,
. . .
value_expr_n when choice_n;
RTL Hardware Design
Chapter 4

37. select_expression choice_i Choices must be Discrete type or 1-D array
With finite possible values
choice_i
A value of the data type
Choices must be
mutually exclusive
all inclusive
others can be used as last choice_i
RTL Hardware Design
Chapter 4

38. E.g., 4-to-1 mux
RTL Hardware Design
Chapter 4

39. Can “11” be used to replace others?
RTL Hardware Design
Chapter 4

40. E.g., 2-to-22 binary decoder
RTL Hardware Design
Chapter 4

41. E.g., 4-to-2 priority encoder
RTL Hardware Design
Chapter 4

42. Can we use ‘-’?
RTL Hardware Design
Chapter 4

43. E.g., simple ALU
RTL Hardware Design
Chapter 4

44. E.g., Truth table
RTL Hardware Design
Chapter 4

45. Conceptual implementation
Achieved by a multiplexing circuit
Abstract (k+1)-to-1 multiplexer
sel is with a data type of (k+1) values: c0, c1, c2, , ck
RTL Hardware Design
Chapter 4

46. select_expression is with a data type of 5 values: c0, c1, c2, c3, c4
RTL Hardware Design
Chapter 4

47. RTL Hardware Design
Chapter 4

48. E.g.,
RTL Hardware Design
Chapter 4

49. 3. Conditional vs. selected signal assignment
Conversion between conditional vs. selected signal assignment
Comparison
RTL Hardware Design
Chapter 4

50. From selected assignment to conditional assignment
RTL Hardware Design
Chapter 4

51. From conditional assignment to selected assignment
RTL Hardware Design
Chapter 4

52. Comparison Selected signal assignment:
good match for a circuit described by a functional table
E.g., binary decoder, multiplexer
Less effective when an input pattern is given a preferential treatment
RTL Hardware Design
Chapter 4

53. Conditional signal assignment:
good match for a circuit a circuit that needs to give preferential treatment for certain conditions or to prioritize the operations
E.g., priority encoder
Can handle complicated conditions. e.g.,
RTL Hardware Design
Chapter 4

54. May “over-specify” for a functional table based circuit. E.g., mux
RTL Hardware Design
Chapter 4

55. MLU Example

56. MLU Block Diagram A MUX_4_1 NEG_A Y NEG_Y B L1 L0 NEG_B MUX_0 A1 Y11 A1 A
MUX_4_1
IN0 Y1
MUX_1 1
NEG_A
IN1
MUX_2 Y
IN2
OUTPUT
IN3
SEL0
SEL1
NEG_Y 1 B1 B L1 L0
MUX_3
NEG_B

57. MLU: Entity Declaration
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mlu IS
PORT(
NEG_A : IN STD_LOGIC;
NEG_B : IN STD_LOGIC;
NEG_Y : IN STD_LOGIC;
A : IN STD_LOGIC;
B : IN STD_LOGIC;
L1 : IN STD_LOGIC;
L0 : IN STD_LOGIC;
Y : OUT STD_LOGIC );
END mlu;

58. MLU: Architecture Declarative Section
ARCHITECTURE mlu_dataflow OF mlu IS
SIGNAL A1 : STD_LOGIC;
SIGNAL B1 : STD_LOGIC;
SIGNAL Y1 : STD_LOGIC;
SIGNAL MUX_0 : STD_LOGIC;
SIGNAL MUX_1 : STD_LOGIC;
SIGNAL MUX_2 : STD_LOGIC;
SIGNAL MUX_3 : STD_LOGIC;
SIGNAL L: STD_LOGIC_VECTOR(1 DOWNTO 0);

59. MLU - Architecture Body
BEGIN
A1<= NOT A WHEN (NEG_A='1') ELSE A;
B1<= NOT B WHEN (NEG_B='1') ELSE B;
Y <= NOT Y1 WHEN (NEG_Y='1') ELSE
Y1;
MUX_0 <= A1 AND B1;
MUX_1 <= A1 OR B1;
MUX_2 <= A1 XOR B1;
MUX_3 <= A1 XNOR B1;
L <= L1 & L0;
with (L) select
Y1 <= MUX_0 WHEN "00",
MUX_1 WHEN "01",
MUX_2 WHEN "10",
MUX_3 WHEN OTHERS;
END mlu_dataflow;

60. Modeling Common Combinational
Logic Components
Using Dataflow VHDL
ECE 448 – FPGA and ASIC Design with VHDL

61. Wires and Buses
ECE 448 – FPGA and ASIC Design with VHDL

62. Signals a b SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC_VECTOR(7 DOWNTO 0); a 1
wire b
bus 8

63. Merging wires and buses4 10 b d 5 c
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
d <= a & b & c;

64. Splitting buses a d b c SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);4 10 d b 5 c
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL c: STD_LOGIC;
SIGNAL d: STD_LOGIC_VECTOR(9 DOWNTO 0);
a <= d(9 downto 6);
b <= d(5 downto 1);
c <= d(0);

65. Fixed Shifters & Rotators
ECE 448 – FPGA and ASIC Design with VHDL

66. Fixed Shift in VHDL A A>>1 AshiftR AshiftR <=
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL AshiftR: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3)
A(2)
A(1)
A(0) A
A>>1
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required.
AshiftR
‘0’
A(3)
A(2)
A(1)
AshiftR <=

67. Fixed Rotation in VHDL A A<<<1 ArotL ArotL <=
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL ArotL: STD_LOGIC_VECTOR(3 DOWNTO 0);
A(3)
A(2)
A(1)
A(0) A
A<<<1
Internal signals are from DUT.
Main process may be split into main process. I.e. one to drive clk, rst and other for test vectors.
Many architectures can be tested by inserting more
for DUT:TestComp use entity work.TestComp(archName) statmetns
“work” is the name of the library that “TestComp” is being compiled to.
The “DUT” tag is required.
ArotL
A(2)
A(1)
A(0)
A(3)
ArotL <=

68. Buffers
ECE 448 – FPGA and ASIC Design with VHDL

69. Tri-state Buffer (a) A tri-state buffer (b) Equivalent circuitx f e
= 0
(a) A tri-state buffer x f e x f e
= 1 x f Z 1 Z 1
(b) Equivalent circuit 1 1 1
(c) Truth table

70. Four types of Tri-state Buffers

71. Tri-state Buffer – example (1)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY tri_state IS
PORT ( ena: IN STD_LOGIC;
input: IN STD_LOGIC;
output: OUT STD_LOGIC );
END tri_state;

72. Tri-state Buffer – example (2)
ARCHITECTURE dataflow OF tri_state IS
BEGIN
output <= input WHEN (ena = ‘1’) ELSE ‘Z’;
END dataflow;

73. Multiplexers
ECE 448 – FPGA and ASIC Design with VHDL

74. 2-to-1 Multiplexer s f s w w f 1 w 1 1 (a) Graphical symbol1 s f w 1 w 1
(a) Graphical symbol
(b) Truth table

75. VHDL code for a 2-to-1 Multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux2to1 IS
PORT ( w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END mux2to1 ;
ARCHITECTURE dataflow OF mux2to1 IS
BEGIN
f <= w0 WHEN s = '0' ELSE w1 ;
END dataflow ;

76. Cascade of two multiplexers3 w 1 y 2 w 1 1 s2 s1

77. VHDL code for a cascade of two multiplexers
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux_cascade IS
PORT ( w1, w2, w3: IN STD_LOGIC ;
s1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END mux_cascade ;
ARCHITECTURE dataflow OF mux2to1 IS
BEGIN
f <= w1 WHEN s1 = ‘1' ELSE
w2 WHEN s2 = ‘1’ ELSE
w3 ;
END dataflow ;

78. 4-to-1 Multiplexer s s s s f 1 1 w 00 w w 01 1 1 w f 1 w 10 2 1 w 2 ws s s f 1 1 w 00 w w 01 1 1 w f 1 w 10 2 1 w 2 w 11 3 1 1 w 3
(a) Graphic symbol
(b) Truth table

79. VHDL code for a 4-to-1 Multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux4to1 IS
PORT ( w0, w1, w2, w3 : IN STD_LOGIC ;
s : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
f : OUT STD_LOGIC ) ;
END mux4to1 ;
ARCHITECTURE dataflow OF mux4to1 IS
BEGIN
WITH s SELECT
f <= w0 WHEN "00",
w1 WHEN "01",
w2 WHEN "10",
w3 WHEN OTHERS ;
END dataflow ;

80. Decoders
ECE 448 – FPGA and ASIC Design with VHDL

81. 2-to-4 Decoder En w w y y y y 1 3 2 1 w y 1 3 1 1 w y 2 1 1 1 y 1 1 13 2 1 w y 1 3 1 1 w y 2 1 1 1 y 1 1 1 1 y En 1 1 1 1 x x
(a) Truth table
(b) Graphical symbol

82. VHDL code for a 2-to-4 Decoder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY dec2to4 IS
PORT ( w : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;
En : IN STD_LOGIC ;
y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;
END dec2to4 ;
ARCHITECTURE dataflow OF dec2to4 IS
SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
Enw <= En & w ;
WITH Enw SELECT
y <= “0001" WHEN "100",
"0010" WHEN "101",
"0100" WHEN "110",
“1000" WHEN "111",
"0000" WHEN OTHERS ;
END dataflow ;

83. Encoders
ECE 448 – FPGA and ASIC Design with VHDL

84. Priority Encoder w y w 1 y 1 w 2 z w 3 d 1 w y z x 2 3

85. VHDL code for a Priority Encoder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY priority IS
PORT ( w : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
y : OUT STD_LOGIC_VECTOR(1 DOWNTO 0) ;
z : OUT STD_LOGIC ) ;
END priority ;
ARCHITECTURE dataflow OF priority IS
BEGIN
y <= "11" WHEN w(3) = '1' ELSE
"10" WHEN w(2) = '1' ELSE
"01" WHEN w(1) = '1' ELSE
"00" ;
z <= '0' WHEN w = "0000" ELSE '1' ;
END dataflow ;