1. BESIII EMC electronics
Jinfan.Chang

2. Outline Introduction: Tasks and Specifications
EMC readout electronic system
384-channel system test results
Run status on BESIII

3. EMC electronics tasks measure the energy deposited in every crystal
provide a fast energy trigger
Provide coarse timing information that can be used to reduce background noise

4. Specifications for EMC electronics
Parameter
Values
Number of channels
6,240
System clock
20.8 MHz
L1 trigger latency
6.4 µs
Maximum single channel hit rate
 1 kHz
Equivalent noise charge (energy)
0.16 fC (200 pF
Integral nonlinearity
 1% (before correction)
Cross talk
 0.3%
Dynamic range
15 bits
Information to trigger
Analog sum of 16 channels
Gain adjustment range for triggers
 20 %

5. EMC electronics system
The system consists of five main parts:
Preamplifiers mounted on the crystals
Post amplifier/shaper NIM modules
Charge digitization VME modules (Q-module)
Test and control VME modules (Test-Control)
Fan-out VME modules (Fan-out)

6. Preamplifiers
Gain
1 mV/fC
Equivalent input noise
700 e
Dynamic range
0.5 to 1,500 fC
Linear output range
up to 2.5 V
Decay time constant
50 s
Power consumption
140 mW
Each preamplifier includes two charge sensitive amplifiers, which mounted on the backs of the photodiodes and were fixed on the crystal with an aluminum shielding box.
The output signals are sent to the post amplifier via 18m shielded twisted pair cables.
Each charge sensitive amplifier is independent. The low voltages of each amplifiers, the bias voltage of each photodiode, and the test pulses are supplied by post amplifier modules

7. Preamplifiers In order to reduce noise
It is important to isolate the preamplifier and aluminum box from detector ground
Preamplifiers are grounded at post amplifier through 18m cables
Well shielding cables

8. Post amplification
The post amplification circuits are implemented as single 6U NIM modules; each has 16 channels.
The two preamplifier outputs are received by two differential amplifiers and then go through a switching stage with two selections. Normally the selection A + B that sums the two photodiode outputs is used. If one photodiode or preamplifier dies, the selection 2A or 2B that boosts the signals by a factor of two is used.
The output of shapers go through the baseline restoration circuit and are then sent by a differential driver to the charge measurement circuits in the Q-module.
Sixteen analog signals from post amplifier channels are sent to a circuit labeled 16 to generate module analog sums. The gain of each channel is adjustable to compensate for the light yield variations of crystals and response differences of photodiodes.

9. Post amplification A V o ( t )
preamplifier
Post amplifier
Q-module
The post amplifier provides semi-Gaussian shaping to reduce noise and pileup
The time constant of the CR-RC shaping circuit is chosen to be 1μs
This shaping time constant is found to be optimum for minimizing system noise

10. Coder and range Selector
Charge digitization
Pipeline
Peak Finding
Buffer
From
post amp
Threshold
Coder and range Selector
16 ÷2 2
FADC
CBLT
VME
The charge digitization and peak finding circuits are implemented as single 9U VME modules; each has 32 channels.
Three 10 bit FADCs are used to achieve the desired 15 bit dynamic range
The sampled data is selected and the 12-bit data are passed through a digital pipeline to obtain proper delay time
Peak values of signals above threshold and an additional 6-bit peaking time are stored in buffers to be read out by VME CBLT mode.

11. Charge digitization
Digital resolution of each range is much better than CsI resolution.
Three 10-bit FADCs with different full scale ranges are used to achieve the desired 15-bit dynamic range
FADC channels with three different gains: 2, 2 and 16. The output of the unsaturated FADC channel that has the highest gain (or lowest range) is selected as valid data by a logic circuit, and a 2-bit range code is added to the data

12. Charge digitization
Peak Finding Timing
4.9
6.4
7.9
9.4
t/ms
Beam Crossing Time
Sampled Signal L1
Peak Finding Time Window
Trigger Latency
Signal Peak Time
Because the shaped signals have a 3 μs peaking time and the FADCs sample rate is 20.8 MHz, two or three data points can be sampled at the peak of the signal pulse, so the peak finding circuit must find the peak value within 3 s after the L1 trigger arrives.
The total delay time of the pipeline is chosen as 4.9μs, which is 1.5μs less than the 6.4μs trigger latency. The waveform peak is in the middle of the 3μs peak finding time window.
Peak timing is used to reject background

13. Test Control and Fan out
Test control module controls the three operation modes of the EMC readout system
collision mode
calibration mode
gain adjustment mode
Collision mode is the regular data acquisition mode when the collider is in operation.
In the calibration mode, the test control module generates a series of test pulses to test each electronics channel. An electronics self check is performed.
The fan out module is the communication between the L1 trigger system and the EMC readout electronics. It receives these signals and distributes them to the 16 Test and Control Modules in the 16 VME crates of the EMC readout system.

14. 384 channels system test 384 preamplifiers 24 post amplifiers
12 Q-modules
1 test control
Calibration mode

15. Calibration pulse test
Calibration pulse was generated by AD768 which is a 16bit DAC chip on the test control module.
Each pulse was measured by ORTEC multichannel analyzer (8192 channels).FWHM less than 1.5
The integral nonlinearity of calibration pulse is less than 0.01%

16. Integral nonlinearity test
Low range：0.128 %
Middle range：0.107 %
High range：0.125 %
384 channels, the average integral nonlinearity of each range is less than 1%

17. Noise test
The equivalent input noise charge (ENC) measurement results of 384 channels, each channel includes two photodiodes and two charge amplifiers
The average ENC per channel is 973 e, with the 80 pF photodiode capacitive loading

18. Run status on BESIII
EMC 6240 channels electronics start installing
16 VME crates with 200 Q-modules
34 NIM crates with 394 Post amplifier
the first cosmic ray event
the first Collision event

19. Electronics temperature
The temperature in barrel can be controlled below 26oC by cooling water.
The temperature will rise when the cooling system problem, but the variation range is less 2DC (from to )
The electronics crate temperature is stable, the variation range is less than 2DC(from to ).
The rack cooling system works well.

20. Electronics calibration
Calibration Y=a0+a1X
Low range a1
The calibration parameters are very stable in the half year(from to )
The stability of calibration parameter a1 is about 0.1%.
middle range a1
High range a1

21. Electronics pedestal the stability of pedestal
the stability of pedestal sigma
The pedestal are also stable during the half year.

22. EMC system noise The data was taken in the condition without beam
The energy of noise was calibrated by BhaBha events.
The average noise of 6240 channels is less than 200KeV.
The EMC threshold is 2.5 times the noise rms.

23. Summary EMC electronics achieve the design requirement
EMC readout electronics have a long term stable running from to now.
Total 6240 channels work well, there is no dead channel so far.
EMC barrel Hitmap histogram of phi and Z profile
endcap Hitmap histogram

24. Thanks！