1. « Floating Point » Charge Sensitive Amplifier
for the focal plane of S3
Good Afternoon every one. I’m Philippe Vallerand from GANIL and I’m going to present you
A Floating Point Charge Sensitive Amplifier .
This new chip is specially dedicated to the S3 projet and it has been designed in collaboration with E.Delagnes from Irfu.
the topic that I present to you is a new design of, called floating point.
This new chip is part of S3 project and it results from a collaboration between Eric Delagnes from IRFU and me from GANIL.
Ph.Vallerand – GANIL
E.Delagnes – IRFU

2. S3 : GANIL/SPIRAL1/SPIRAL2 facility SPIRAL2 Phase 1 The accelerator
SPIRAL2 is one of the ESFRI list projects (40 most important EU research infrastructure projects)
SPIRAL2 Phase 1
The accelerator
S3 :
studies of heavy and super heavy elements produced using the stable ion beam at very high intensity
Existing GANIL
First of all, let me speak about the S3 project in few words and its implementation in SPIRAL2 projet at GANIL.
This Super Separator Spectrometer S3 is dedicated to the studies of heavy and super heavy elements produced using the stable ion beam at very high intensity.
These beams will be delivered by the linear accelerator at GANIL designed in the framework of the SPIRAL2 project.
S3 (Super Separator Spectrometer) is a device designed for experiments with the very high intensity stable beams of SPIRAL2. These heavy ions (from He to Ca in a first step, then up to U), will reach intensities from 1pµA up to 1pmA
S3 will be set-up at the exit of the linear accelerator LINAG at GANIL (Caen, France), in the scope of the SPIRAL2 project. 2

3. Super Separator Spectrometer S3
Preliminary draft of the design S3
Final
focal plane
Low Energy
Medium Energy
High Energy
(The principle of S3 is the following : )
In fact, the primary beam provided by the linear accelerator will hit on a primary target.
The separation of the beam will be done in two steps,
the first being a high rejection device and an appropriate beam stopper.
After this first step, ions of interest could, if necessary, react on a secondary target.
Next to this point, a secondary spectrometer help with separation if very high purity is needed.
The final focal plane can be equipped with the relevant detection system. 3

4. Focal plane detector setup
To study the stopped recoil
Tunnel of Silicon Detectors
for backward emitted alpha, electrons and X-rays
Germanium detector
Array
Implantation detector :
Double Sided Silicon Strip Detector
for energy and time measurements of heavy ions,  and e- decay particles
Time of flight Tracking detector
Secondary electron devices for position & time measurements
More in detail, this focal plane detector is composed by several detection devices
which are needed to study the stopped recoil.
Recoil will first go through a time of flight tracking detector based on secondary electron devices for position and time measurements.
Recoil is then deposited in a implantation detector based on a Double Sided Silicon Strip Detector.
for energy and time measurement of heavy ions,  and e- decay particles.
This detector will be surrounded by a tunnel of Silicon detectors for charge particle and Germanium detector array for neutrons particles.
(alpha,electrons and protons, escaping the implantation silicon following recoil decay process. The silicon detectors will be surrounded by a Germanium array constituted by Exogam clovers. 4

5. Implantation Silicon Detector
Technical Specifications
heavy ion 
10 µs
Number of channels : 256
Counting rate / channel : 10 kHz
Energy range :
100 keV to 15 MeV with a resolution ~ 15keV FWHM
10 MeV to 500 MeV with a resolution ~ 1% FWHM
challenge
2 challenges
2) Dynamic range ~ 80,000 = bits rms
1) Accurate measurement of an  decay particle of 10 MeV few 10 µs after the huge energy deposition related to the heavy ion implantation in the same strip.
Let’s see now, the technical specifications of the implantation Silicon Detector :
Precisely, it is composed by 256 channels
and the counting rate per channel is expected about 10 kHz.
Concerning the energy measurement,
3 ranges are identified
One for the energy from 100 keV to 15 MeV with a resolution ~ 15keV FWHM
The second one for the energy from 10 MeV to 500 MeV with a resolution ~ 1% FWHM
And a third for the energy from -7.5 MeV to -250 keV resolution not defined?
For the electronics, as you can see on this picture,
the real challenge is to measure accurately an alpha decay particle of 10 MeV few 10 microseconds after the huge energy deposition related to the heavy ion implantation in the same strip.
 and this energy measurement is to be carryed out in a dynamic range of ~ = bits 5

6. Electronic Challenges
How to provide this dynamic range of 80,000 with only one channel of low cost BE Electronics (14 bits) ?
Reminders :
Offering a dynamic range of 80,000 is possible with discrete CSA but requires 2 channels of Back End Electronics of 14 bits
An integrated CSA in 3.3V technology can’t offer a dynamic range of 80,000 !! but easy to integrate several channels in a same chip
Innovation is required
CSA based on a dynamic configuration of the gain : « Floating Point  » CSA
Moreover, it is important to take account of an another constaint namely (as) the cost of the electronic chain.
That’s why the the global question is
How to provide this dynamic range of with only one channel of BE Electronics low cost using for exemple a flash ADC 14 bits?
I remind you that
in discrete electronics, a dynamic range of for a CSA is possible but requires 2 channels Back End Electronics of 14 bits.
Whereas In microelectronics, a 3.3v technology for exemple can’t offer a dynamic range of !!
but permit easily to integrate several channels in a same chip
For this reasons, innovation of a new architecture is required !!
And in this way, we have designed a charge sensitive amplifier based on a dynamic configuration of the gain called « Float Point  » CSA 6

7. Principle of the Floating Point CSA
Adapt the CSA gain to the energy
to be measured in real time :
 a high gain for low energy ~ 44.4 mV/MeV (Cf = 1pF)
 a low gain for high energy ~ 2.1 mV/MeV (Cf = 21pF)
2 gains
detector
ADC
only one output to digitalize
switching a feedback capacitor for changing the gain as a function of output signal level
Let’s see in details the principle of this FPCSA.
In fact, the principle is to adapt the CSA gain to the energy to be measured in real time
Precisely, only two gains are enough to cover all the dynamic range
A first One is a High gain for Low Energy ~ 44.4 mV/MeV obtained with a feedback capacitor of 1pF
A second one is a Low gain for High Energy ~ 2.1 mV/MeV obtained with a feedback capacitor of 21 pF
Based on a standard CSA illustrated on this picture, the concept consists in switching feedback capacitors as a function of output signal level which is added in parallel to the preamplifier.
It is important to mention that with this CSA, only one output to digitalize is needed. 7

8. Principle of the Floating Point CSA
Block diagram of the Floating Point CSA
Allowing a return of the CSA output signal to the baseline in less than the specified 10µs, with a drawback of parallel noise. Time constant is supposed to be cancelled after digitization
Set-up for simulations :
35kΩ
21pF
700kΩ
1pF
60pF
detector + cable
capacitor
CSA_output(t)
threshold
As you can see on this block diagram of the floating point CSA, a comparator and a monostable are used to analyse the signal output and to drive the swiching feedback capacitor.
In fact, At reset, (or in steady state conditions), the CSA starts with a high gain configuration.
When the output signal don’t reach the threshold, it has a typical shape (which is known for a CSA).
When the output signal reaches a high level threshold, a low gain capacitor is added in parallel to the other.
Consequently, the gain of the CSA changes and the output signal decreases quickly in few nano seconds and
settles to its final value.
(A logical output “low gain” indicates if a low gain event was detected. )
Concerning the set-up for the simulations, the 2 gains have the same relatively short time constant of 700ns allowing a return of the CSA output signal to the baseline in less than the specified 10µs, with a drawback of parallel noise. This time constant is supposed to be cancelled after digitization.
Also, the equivalent capacitor of the detector and his cable are evaluated to 60pf in the worst case. t
time
constant
of 700ns
Low Gain : Rf=35KΩ ; Cf=21pF
High Gain : Rf=700KΩ ; Cf=1pF
Discri output
Cmd_LG
2.4ms 8 t

9. typical shape of the output signal
Simulation results
Transcient simulations
Operation : single pulse energy scan from 1MeV to 33MeV
FPCSA output
in V
30 MeV HG
typical shape of the output signal
25 MeV HG
20 MeV HG
15 MeV HG
10 MeV HG
Let’s see now the simulation results and firstly the transcient simulations.
The first one is a single pulse energy scan from 1 MeV to 33 Mev.
As you can see on this curves, the FPCSA output has a typical shape with
a rise time of fews nano second and a time constant of about 700ns.
5 MeV HG
1 MeV HG
time (s) 9

10. atypical shape of the output signal
Simulation results
Transcient simulations
Operation : single pulse energy scan from 35MeV to 500MeV
FPCSA output
in V
atypical shape of the output signal
500 MeV LG
400 MeV LG
300 MeV LG
digital treatment
required
The second one is a single pulse energy from 35MeV to 500MeV.
The shape of the signal is really atypical for a charge sensitive amplifier.
In fact, while the signal is inferior to the discri level defined to 2 volt, the signal goes up.
In this cases, when the output signal reaches the threshold defined to 2 volts, the signal decreases quickly in few nano seconds and settles to its final value in about 30ns.
It’s clear that the first part of this signals is not exploitable.
That why we consider using a digital treatment in order to remove the whole unusable points.
200 MeV LG
100 MeV LG
50 MeV LG
35 MeV LG
time (s) 10

11. Simulation results ENC ~ 3.2 keV rms  7.2keV FWHM
Noise simulations : CR-RC2 filtering
Equivalent Noise Charge vs peaking time for High Gain
ENC eV
ENC ~ 6.5 keV rms
ENC ~ 3.2 keV rms
 7.2keV FWHM
Let’s pass now to the noise simulations obtained with a CR-RC2.
On this graph we can see the equivalent noise versus the peaking time for high gain.
The optimal equivalent noise charge is obtained for the peaking time of about 500ns.
And his value is about 3.2keV rms equivalent to 7.2keV FWHM.
Rf=700KΩ
Cf=1pF
ENC ~ 3.2 keV rms
peaking time in s 11

12. Simulation results ENC ~ 9.6 keV rms  23keV FWHM
Noise simulations : CR-RC2 filtering
Equivalent Noise Charge vs peaking time for Low Gain
ENC eV
ENC ~ 13.3 keV rms
ENC ~ 9.6 keV rms
 23keV FWHM
For the equivalent noise versus the peaking time for low gain,
the optimal equivalent noise charge is obtained for the peaking time of about 200ns.
and his value is about 9.6 keV rms equivalent to 23 keV FWHM.
Rf=35KΩ
Cf=21pF
ENC ~ 9.6 keV rms
Peaking time (s) 12

13. INL (Measure - Fit)  24.10-3 %  8.6keV
Simulation results
Integrated Non-Linearity simulations
High gain for low energy from 1 to 36MeV
in V
In terms of the integrated Non-linearity,
Concerning the high gain for the low energy from 1 to 36MeV
The integrated Non Linearity obtained is about % equivalent to 8.6 keV, better to the resolution required
energy (MeV)
INL (Measure - Fit)  %  8.6keV 13

14. INL (Measure - Fit)  33.10-2 %  1.6MeV
Simulation results
Integrated Non-Linearity simulations
Low gain for high energy from 36 to 500MeV
in V
Concerning the low gain for the high energy from 36MeV to 500MeV
The integrated Non Linearity obtained is about % equivalent to 1.6MeV better than the 1% required
energy (MeV)
INL (Measure - Fit)  %  1.6MeV 14

15. Prototype chip 2 channel prototype ASIC one channel : 500 µm x 1100 µm
Process : AMS CMOS 0.35µm
Die : 1800 µm x 1900 µm
area ~ 3.3 mm2
one channel : 500 µm x 1100 µm
packaged
in a 44-pin ceramic CQFP.
In view of this encouraging simulations results, a 2 channel prototype ASIC has been designed in AMS CMOS 0.35 micrometer technology
that you can see on this picture.
The size of one channel is about 500 micrometer by 1100 micrometer for one channel.
And also this chip has been packaged in a 44 pin ceramic CQFP packaging
Which is illustrated here 15

16. Characteristics Datasheet
Prototype chip
Characteristics Datasheet
Number of channels: 2
Configurable gains for low energy
44.4 or 88.8 mV/MeV
Configurable gains for high energy
2.1 or 4.2 mV/MeV
Threshold for HG-LG transition (V)
Tuning of the CSA output offset
Tuning of the buffer output offset
Tuning Pulse Low Gain
500ns to 50μs
CSA Output
Differential Analog
LG Output
LVDS
Power consumption per channel
60mW
, at the level of the characteristics datasheet , it is important to note that
For low energy, two configurable gains are available namely 44.4 or 88.8 mV/Mev
For high energy, two configurable gains are available namely 2.1 or 4.2 mV/Mev
Also, severals tuning are available as
The Threshold for High Gain-Low Gain transistion (V) is adjustable
The tuning of the CSA out offset is adjustable
The tuning of the CSA buffer output offset
And The tuning pulse LG are adjustable
Finally, The CSA Output is available in differential mode
And the LG output available in LVDS Standard
As regards the Power consumption per channel, it is about 60milli Watt 16

17. CONCLUSION « floating point » Charge Sensitive Amplifier
Simulation results in agreement with S3 focal plane requirements, specially in terms of resolution needed for a large dynamic range …. to be confirmed more in details
with a specific digital filtering mainly for the low gain
Floating Point CSA architecture : a good compromise in terms of performances, complexity, cost and integration
Chips received few weeks ago
Prototype testing expected at the end of 2011
Next step :
To conclude, (as I have persented during my talk),
- The simulation results are in agreement with the S3 focal plane requirements,
specially in terms of resolution needed for a large dynamic range.
Results which need to be confirmed more in details with a specific digital filtering mainly for the low gain.
- Also, the Floating Point CSA architecture is a good compromise in terms of performances, complexity, cost and integration
Finally, the chips received few weeks ago will be tested at the end of 2011
(And For the next step to follow,)
The Prototype testing is expected at the end of 2011 17

18. Thanks for your attention !
Ph.Vallerand – GANIL
E.Delagnes – IRFU

19. Simulation results Transcient simulations in V time (s)
Operation : single pulse energy scan from -250keV to -7.5MeV
FPCSA output
-250keV HG
in V
-500keV HG
-1 MeV HG
-3 MeV HG
The third one is a single pulse energy from -250keV to -7.5MeV.
As you can see, the shape of the output signal is also standard as for the positive low energy.
-7.5 MeV HG
time (s) 19

20. V  22µV  500 eV Simulation results Transcient simulations in V
Operation : High Energy scan 50MeV to 500Mev
followed by 5MeV
in V
FPCSA output
V  22µV  500 eV
The last transcient simulation shows how a heavy ion in fonction of his deposited energy can cause a degradation on the measurement of an alpha decay particle 10µ second after.
As a result, the simulation about this effect shows a delta V of about 22micro Volt equivalent to 500eV
time (s) 20