1. ELEC 7770 Advanced VLSI Design Spring 2016 Timing Verification and Optimization
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University, Auburn, AL 36849
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

2. ELEC 7770: Advanced VLSI Design (Agrawal)
Proof of Correctness
Static timing analysis proves the timing correctness. That is, the circuit is guaranteed to work at the clock rate determined by the critical path.
But the circuit may also work correctly at faster speeds.
Because the critical path identified by STA (static timing analysis) may be a “false path”.
STA overestimates the delay of the circuit.
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

3. Static Path Sensitization
Definition: Propagation of a signal value through a path to a primary output.
Example: 1
Sensitized path
Stuck-at faults here
are testable
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

4. Statically Unsensitized Path
Definition: Signal cannot be propagated through a unsensitized path.
Cause: Off-path inputs cannot be set to required values.
Example: Off-path inputs
0 or 1
Stuck-at faults here
are not testable
Unensitized path
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

5. Dynamically Sensitized Path
Definition: A dynamic signal can be propagated through a statically unsensitizable path.
Example: See later.
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

6. ELEC 7770: Advanced VLSI Design (Agrawal)
False and True Paths
A false path cannot propagate an event and hence cannot affect the timing of the circuit. False paths are dynamically unsensitizable.
Dynamically sensitizable path (true path): All off-path inputs must settle down to their non-controlling values when the event propagates through the path.
True path of length 3 e d y 1 a 2 1 1 1 3 1 z f 1 b 1 4 c
True path of
length 4
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

7. Static Sensitization of Path
Static sensitization of path: All off-path inputs can be simultaneously set to their non-controlling values.
Longest path in the following example is statically unsensitizable. Such paths are often referred to, though not correctly (why?), as false paths.
True path of length 3 d e y 1 a 2 1 1 1 3 1 1 z 1 f b 1
False path of
length 4
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

8. ELEC 7770: Advanced VLSI Design (Agrawal)
An Example
Statically unsensitizable (false) path.
P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design, Springer, 1991.
False path of delay 3 a e 1 1 g d 1 1 f 1 b c
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

9. ELEC 7770: Advanced VLSI Design (Agrawal)
Example (Cont.)
Another statically unsensitizable false path.
P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design, Springer, 1991. 1
Two false paths of delay 3 a e 1 1 g d 1 f 1 b c
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

10. ELEC 7770: Advanced VLSI Design (Agrawal)
Example (Cont.)
Two paths are dynamically sensitizable and will affect the timing if both are together faulty.
P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design, Springer, 1991.
False paths of delay 3 a e 1
2 3 1 g d 1 f 1 b c
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

11. Static Sensitization Conditionx y z
Off-path inputs
There must exist an input vector (PI) that satisfies the following conditions:
∂y/∂x = 1,
∂z/∂y = 1, . . .
Where ∂y/∂x = y(x=1, PI)  y(x=0, PI) is Boolean difference
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

12. ELEC 7770: Advanced VLSI Design (Agrawal)
An ATPG Method x y z
Stuck-at-0
Path is false if this
fault is redundant
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

13. Optimism and Pessimism
Dynamically
sensitizable
paths
Statically
sensitizable
Paths
(optimistic)
Structural paths analyzed by STA (pessimistic)
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

14. ELEC 7770: Advanced VLSI Design (Agrawal)
Theorem 1
Every statically sensitizable path is dynamically sensitizable.
Proof: Since a vector exists to sensitize the path, if that vector does not specify the path input, then toggling the primary input at the origin of the path will propagate an event through the path.
P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design, Springer, 1991, p. 35.
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

15. ELEC 7770: Advanced VLSI Design (Agrawal)
Theorem 2
The longest path in a circuit is dynamically sensitizable iff it is statically sensitizable.
Proof: Because this is the longest path, all off-path inputs will settle to their sensitizing values at the inputs of any gate before the on-path event propagates through that gate.
P. C. McGeer and R. K. Brayton, Integrating Functional and Temporal Domains in Logic Design, Springer, 1991, p. 37.
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

16. ELEC 7770: Advanced VLSI Design (Agrawal)
Proof of Theorem 2
Case 1: Static sensitization does not specify the value at the path origin.
Toggling the path origin will propagate an event through the path causing dynamic sensitization.
Example: 1
A 01 or 10
here will propagate
through the path
Statically sensitized longest path
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

17. Proof of Theorem 2 (Cont.)
Case 2: Static sensitization specifies the value at the path origin.
Toggling the path origin will propagate an event through the path causing dynamic sensitization because the event on the longest path will see all gates sensitized through shorter paths.
Example:
This event
propagated
through
longest path
Shorter path sets this to
1 before the event arrives on
the longest path 01 01
Statically sensitized longest path
Apply 10 event here
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

18. Proof of Theorem 2 (Cont.)
Case 3: Longest path is statically unsensitizable.
Toggling the path origin will not propagate any event through the path. Toggling other input only dynamically sensitizes shorter path.
Example:
This event did
not propagate
through
longest path
Shorter paths set these to
01 before the event arrives on
the longest path 01 01 10 01 01
Statically unsensitizable longest path
Apply events
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

19. ELEC 7770: Advanced VLSI Design (Agrawal)
Speeding Up a Circuit
False path w 2 a w u v x y z 2 x u a 3 z 2 v 2 y 2
time
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

20. ELEC 7770: Advanced VLSI Design (Agrawal)
Speeding Up a Circuit
False path w 2 a w u v x y z 2 x u a 3 z 2 v 2 y 2
time
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

21. ELEC 7770: Advanced VLSI Design (Agrawal)
Speeding Up a Circuit
Reducing the delay of a false path can increase circuit delay. w 2 a w u v x y z 2 x u a 1 z 2 v 2 y 2
time
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

22. ELEC 7770: Advanced VLSI Design (Agrawal)
Speeding Up a Circuit
False path w 2 a w u v x y z 2 x u a 1 z 2 v 2 y 2
time
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

23. A Delay Optimization Algorithm
REDUCE_DELAY (Circuit graph (V, E), ε)
Repeat {
Compute critical paths and critical delay Δ
Set output data ready time to Δ
Compute slacks
U = vertex subset with slack < ε
W = select vertices in U
Apply transformation to vertices in W
} until (no transformation can reduce Δ) }
G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, p. 427.
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

24. Example: Critical Path Delay
Compute data ready time from input to output a b c d e g 2 3 2 1 11 8 2 x y 2 1 9 3 3 5 6 2 1 8 2
Critical path delay, Δ = 11
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

25. Example: Gate Slack Calculation (1)
Maximum time from input a b c d e g 2 3 2 1 11 8 2 x y 2 1 9 3 3 5 6 2 1 8 2
Critical path delay, Δ = 11
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

26. Example: Gate Slack Calculation (2)
Maximum time to output a b c d e g 8 2 3 2 1 6 5 11 8 8 2 x y 8 2 1 11 3 9 3 3 2 5 6 2 1 6 5 8 8 2 2
Critical path delay, Δ = 11
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

27. Example: Gate Slack Calculation (3)2
Delay of longest path through gate 2 a b c d e g 8 8 8 8 2 3 8 2 1 11 6 5 11 11 11 8 8 2 x y 2 1 11 8 11 3 9 11 3 3 11 2 5 6 2 1 6 5 8 8 8 8 2 2 2
Critical path delay, Δ = 11
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

28. Example: Gate Slack Calculation (4)
Gate slack = Δ – Delay of longest path through gate 2 9 a b c d e g 3 8 8 8 3 3 2 1 11 3 8 11 11 2 x y 2 1 11 11 11 3 11 2 1 8 3 8 3 9 2 2
Critical path delay, Δ = 11
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

29. ELEC 7770: Advanced VLSI Design (Agrawal)
Speeding Up 9 a b c d e g 3 3 3 2 1 3 2 x y U 2 1 3
Split critical path 2 1 3 3 9 2
Critical path delay, Δ = 11
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

30. ELEC 7770: Advanced VLSI Design (Agrawal)
Split Critical Path a b c d e g 2 1 V 1 1 2 1 2 1
U = 0 x y V 2 2 1
U = 1 V aV 3 U 2 1
0 or 1 2
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

31. Synthesize Multiplexer1 U 2 U U 2 x U 2 x U 2 2 aV aV U 2 x aV
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

32. ELEC 7770: Advanced VLSI Design (Agrawal)
Split Critical Path a b c d e g aV aV V 2 1 2 1 2 X y
Δ = 8 3 U 2 1 2
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

33. Alternative Transformation (1)b c d e g 2 1 2 x y 2 1 3 2 1 2
Δ = 11
x = a’ + b’ + c’ + d’ + e’
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

34. Alternative Transformation (2)b c d e g 2 1 2 x y 2 1 3
Isolate and resynthesize 2 1 2
Δ = 11
x = a’ + b’ + c’ + d’ + e’, all inputs are symmetric.
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

35. Alternative Transformation (3)d b c a e g 3 2 1 2 x y 2 1 2 1 2 1 2
Δ = 8
x = a’ + b’ + c’ + d’ + e’, a and d are interchanged.
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

36. 32-bit Ripple-Carry AdderΔ c0 a0 b0
sum0
Δ = delay of one full adder
FA0
sum1 a1 b1
FA1
sum2 a2 b2
FA2
sum31
FA31
a31
b31
c31
32Δ
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

37. One-Bit Full-Adder Circuit
FAi
XOR
sumi ai
XOR
AND bi
AND OR
Ci+1
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

38. ELEC 7770: Advanced VLSI Design (Agrawal)
Speeding Up the Adder
16-bit
ripple
carry
adder
a0-a15
b0-b15
cin
sum0-sum15
a16-a31
16-bit
ripple
carry
adder
b16-b31
Multiplexer
sum16-sum31, c31
a16-a31
16-bit
ripple
carry
adder 1
b16-b31
This is a carry-select adder 1
Spring 2016, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)