1. Chapter 1 and 2 review CMOS Devices and models Fabrication process
Diodes
Transistors
Resistors
Capacitors
Fabrication process
Layout

2. Capacitors conductor-insulator-conductor
C = C0A or C0L
Poly-poly cap
Fringe cap
Chapter 1 Figure 37

3. MOS cap: for NMOS, connect D, S, B and gnd together, G free;
for PMOS, connect D, S, and well together, both terminals free.
Chapter 1 Figure 36
There are many more capacitors (any time you have conductor-insulator-conductor). Most are parasitic. Most are nonlinear.

4. Resistors R = R*(# of squares)  Rs*(L/W)
Chapter 1 Figure 34
Types of sheet materials: poly1, poly2, metals, well, diffusion, substrate
transistors (channel inversion layer)

5. Example: well resistor
Chapter 1 Figure 35

6. MOSIS ON 0.5 um process

7. Diodes
Chapter 1 Figure 01
n-well
Layout view: p+ n+

8. Cj junction capacitance tT depends on materials
Large signal model:
gd = ID/VT, rd = 1/gd
Cd = tT*ID/VT
Cj junction capacitance
tT depends on materials
I_d = I_s * exp(V_d/(kT/q) -1)
Small signal model:
Chapter 1 Figure 04
Cd, Cj, gd all depend on bias voltage VD
For reverse bias, gd = 0

9. NMOS transistor
Chapter 1 Figure 10 G S D B

10. Square law model: DC large signal
triode
saturation
On state: Veff >0:
= VGS – Vtn
deep triode
Off state: Veff <=0: ID = 0 for all VDS.

11. Small signal model: low freq
Chapter 1 Figure 17

12. NMOS with parasitic caps
Chapter 1 Figure 21

13. Frequency dependent model
Chapter 1 Figure 22

14. Key MOS parameters Intrinsic gain: A0 = gmrds = gm/gds
Chapter 1 Figure 26

15. Key MOS parameters
Transit frequency: frequency at which current gain reduces to unity
Chapter 1 Figure 27
vgss(Cgs+Cgd)=
When |Iin| = |Iout| : wT = gm/(Cgs+Cgd)  gm/Cgs

16. Mobility limited, linear in Vgs
Chapter 1 Figure 30
Subthreshold
Weak inversion

17. Chapter 1 Figure 28

18. Chapter 1 Table 01

19. Chapter 1 Table 04