1. Final Exam Review
CSE 241
B.Ramamurthy
12/5/2018
B.Ramamurthy

2. Place and Time Date: 12/11/2013 Time: 8.00 – 11.00 AM Place: Cooke 121
Please bring
Pencils, pens and erasers.
Closed book exam
12/5/2018
B.Ramamurthy

3. Topics
Chapter 4: HDL Models of combinational circuit: Gate level modeling and behavioral modeling:
Chapter 5: Sequential circuit analysis: pages
Chapter 5: Synthesizable HDL models of sequential circuits: pages , p
Chapter 5: Sequential circuit design: p.236-p.245
All the homework problems
12/5/2018
B.Ramamurthy

4. How do I study? Help!
Writing a test bench: pages , read every line of these pages, and understand Example 4.10 on p.181
From state diagram to Verilog HDL simulation: see example on p.229, only state diagram based model and ONLY its test bench on the next page (p.230)
Analysis example: see figure 5.18, table 5.4, up to figure 5.19 on p.214
Design example; p : figure 5.27, table 5.11, figure 5.28, figure 5.29
Counter design: figure 5.32, table 5.14, figure 5.33, figure 5.34
12/5/2018
B.Ramamurthy

5. Format & possible questions
Sequential circuit analysis
Sequential circuit design
Counter design
Verilog HDL verification (means test bench included) of combinational circuits
Verilog HDL verification of sequential circuits
12/5/2018
B.Ramamurthy

6. Remember… Learn from the home works assigned
Find ways to efficiently answer questions
Find ways to not make silly mistakes
Create a mental checklist to make sure you have not missed anything important on the exam (like your name of the exam paper!)
Read the question paper and strategize on the order in which you will answer the questions
Come prepared: there is no substitute for hard work
Build up competencies and not deficiencies…
Good luck.
12/5/2018
B.Ramamurthy