1. Lecture 29: Virtual Memory-Address Translation

2. Review:Address translation via Page Table

3. Review: Typical Page Table Entry
Present/absent: 1 if the page is in memory
Protection: what operations to the page are allowed
Modified: 1 if the page is modified since it is loaded. Also called
“dirty” bit
Referenced: 1 if the page is read or written
Caching disabled: 1 if disabling caching this page

4. Two problems of page table
Speed
Address translation is for every memory access
Large page tables

5. Speeding up Address Translations
Translation Lookaside Buffer = Page Table Cache
Frequent page table entries in the high-speed cache – TLB hit
Rest will go to slower-speed memory – TLB miss

6. TLBs – Translation Lookaside Buffers
Speeds up paging by caching recent address translations
Typically small size – a few 10s of entries
TLB Hit rates are very important for performance

7. TLB is Associative Register
Associative registers – parallel search
Address translation (A´, A´´)
If A´ is in associative register, get frame # out.
Otherwise get frame # from page table in memory
This is done by the OS, and takes some time
Page #
Frame #

8. Large page tables
Multi-level page tables
Inverted page tables

9. Page-Table Size Consider a full 232-byte address space
assume 4096-byte (212-byte) pages
4 bytes per page table entry
the page table would consist of 232/212 (= 220) entries
its size would be 222 bytes (or 4 megabytes)
Imagine 264-byte address space
Before we get too excited about page tables, we need to determine what they cost and, in particular, how much memory is used merely to hold the page table. The picture computes the size of a page table for a 32-bit address space with 4K pages—4 megabytes. This is probably far too much memory to waste on a purely overhead function. What is needed is some technique for putting the page table itself into some form of virtual memory.
Copyright © 2002 Thomas W. Doeppner. All rights reserved.

10. Multi Level Page Tables1
1023 2 1
1023 2 10 10 12 1
1023 2
Level 1
2 level page table
32 bit address split as 10, 10, 12
Level 2

11. Multi Level Page Tables
Address 1
1023 2 10 10 12 2
1020 1 1
1023 2
Level 1
Validity bit
Level 2

12. Multi Level Page Tables1
1023 2
Address 1 2
1020
Page fault!
2nd level page table not in memory. 1
Level 1
Validity bit
Level 2

13. Multi Level Page Tables
page fault! 1
1023 2
Address 1
1023 2 1 2
1020 1 1
Level 1
Fetch into memory
Validity bit
Level 2

14. Space Efficiency 1023 2 1 Level 1 Level 21
1023 2 1
1023 2 1
1023 2
Level 1 1
1023 2
Suppose only pages 0,1 and 1023 in the level 1 table were used
Only those three 2nd level page tables need exist
Level 2

15. One entry for each page of physical memory
Inverted Page Tables
One entry for each page of physical memory
Virtual
Address
Page #
Offset
Page Frame Table
Hash Table
Here, inverted page tables, a variant of hashed page tables, are used to avoid wasting a large amount of memory for the translation map. A page frame table is maintained that indicates for each page frame of real memory what virtual address is mapped into it. In a typical implementation (we describe here a simplification of the IBM RS/6000 scheme), the hardware takes the page number from the virtual address, hashes this into a hash table, and then follows a linked list of hash synonyms in the page-frame table until it finds the desired entry. Then the index of this entry (in the page-frame table) is the page-frame number of the page. If the entry is not found, then a page fault is generated.
This procedure would be quite slow if it were always performed exactly as described. However, it can be combined with the use of a TLB to achieve a system that, on the average, performs well.
Another difficulty with inverted page tables is that there are usually portions of several address spaces in primary storage. Thus the virtual address of a page does not identify it uniquely, since different address spaces have pages with identical virtual addresses. So there must be some sort of address space ID to indicate which page is whose. There is a hardware register that contains the address space ID of the current address space, and each entry in the page-frame table contains an address space ID.
Copyright © 2002 Thomas W. Doeppner. All rights reserved.

16. Page Size Usually 4KB or greater Too large – internal fragmentation
Half of the last page is probably wasted
Too small – number of pages increase
Larger page table
Greater overhead in transferring to/from disk