1. Instructor: Alexander Stoytchev
CprE 281: Digital Logic
Instructor: Alexander Stoytchev

2. Simple Processor CprE 281: Digital Logic
Iowa State University, Ames, IA
Copyright © Alexander Stoytchev

3. Administrative Stuff Final Project (7% of your grade)
Posted on the class web page (Labs section)
This is due this week (during your lab)

4. Administrative Stuff The FINAL exam is scheduled for
Thursday May 2:15-4:15 PM
It will be in this room.

6. Final Exam Format
The exam will cover: Chapter 1 to Chapter 6, and Sections
Emphasis will be on Chapter 6 and Chapter 5
The exam will be open book and open notes (you can bring up to 5 pages of handwritten notes) plus your textbook.

7. Final Exam Format The exam will be out of 130 points
You need 95 points to get an A
It will be great if you can score more than 100 points.
but you can’t roll over your extra points 

8. Topics for the Final Exam
K-maps for 2, 3, and 4 variables
Multiplexers (circuits and function)
Synthesis of logic functions using multiplexers
Shannon’s Expansion Theorem
1’s complement and 2’s complement representation
Addition and subtraction of binary numbers
Circuits for adding and subtracting
Serial adder
Latches (circuits, behavior, timing diagrams)
Flip-Flops (circuits, behavior, timing diagrams)
Counters
Registers

9. Topics for the Final Exam
Synchronous Sequential Circuits
FSMs
Moore Machine
Mealy Machines
State diagrams, state tables, state-assigned tables
State minimization
Designing a counter
Arbiter Circuits
Reverse engineering a circuit
ASM Charts
Register Machines
Bus structure and Simple Processors
Something from Star Wars

10. How to Study for the Final Exam
Form a study group
Go over the slides for this class
Go over the problems at the end of Ch 5 & 6
Exercise
Get some sleep

11. Digital System Datapath circuit Control circuit To store data
To manipulate data
To transfer data from one part of the system to another
Comprise building blocks such as registers, shift registers, counters, multipliers, decoders, encoders, adders, etc.
Control circuit
Controls the operation of the datapath circuit
Designed as a FSM

12. A Simple Processor
[ Figure 7.9 from the textbook ]

13. What are the components?
[ Figure 7.9 from the textbook ]

14. Register R0
[ Figure 7.9 from the textbook ]

15. All Registers
[ Figure 7.9 from the textbook ]

16. 2-Bit Register
IN1
IN0
OUT1
OUT0 1

17. 4-Bit parallel-access shift register
(this one is not used in this example)
[ Figure 5.18 from the textbook ]

18. Tri-State Driver
[ Figure 7.9 from the textbook ]

19. All Tri-State Drivers
[ Figure 7.9 from the textbook ]

20. Tri-state driver (see Appendix B for more details)
[ Figure 7.1 from the textbook ]

21. Bus Structure
A way to transfer data from any register (device) to any other register (device)
A set of n wires to transfer an n-bit data
What if two registers write to the bus at the same time? n
Bus

22. Figure 7.1. Tri-state driver.
Also called tri-state buffer
Z: High impedance state
Figure 7.1. Tri-state driver.
device3
device2
device1
device0
Then several devices can be connected to a single wire
Note that at any time, at most one of e0, e1, e2, and e3 can be set to 1 e2 e3 e1 e0

23. An n-bit Tri-State Driver
An n-bit tri-state buffer can be constructed using n 1-bit
tri-state buffers.
Input e e e e e
Output

24. A digital system with k registers
[ Figure 7.2 from the textbook ]

25. How to connect registers to a bus (using tri-state drivers)
This shows only two 2-bit registers, but this design scales to more and larger registers.
[ Figure 7.3 from the textbook ]

26. An alternative approach uses multiplexers to implement a bus
[ Figure 7.4 from the textbook ]

27. An alternative approach uses multiplexers to implement a bus
(eight 5-to-1 multiplexers)
This requires one multiplexer per bit.
Assuming 8-bit registers, we need eight 5-to-1 multiplexers.
[ Figure 7.4 from the textbook ]

28. Adder/Subtractor
[ Figure 7.9 from the textbook ]

29. Adder/subtractor unity y y n – 1 1
Add
Sub
control x x x n – 1 1 c n
-bit adder c n s s s n – 1 1
[ Figure 3.12 from the textbook ]

30. The first two stages of a carry-lookahead adderx 1 y g p s c 2
[ Figure 3.15 from the textbook ]

31. A hierarchical carry-lookahead adder
Block x 15 8 – y 7 3 1
Second-level lookahead c s P G 31 24 16 32
[ Figure 3.17 from the textbook ]

32. Control Circuit
[ Figure 7.9 from the textbook ]

33. Designing The Control Circuit

34. The function register and decoders
Clock X w En y 1 2 3
2-to-4 decoder
Function Register Y I FR in f Rx Ry
Function
[ Figure 7.11 from the textbook ]

35. Operations performed by this processor
Function Performed
Load Rx, Data
Rx  Data
Move Rx, Ry
Rx  [Ry]
Add Rx, Ry
Rx  [Rx] + [Ry]
Sub Rx, Ry
Rx  [Rx] - [Ry]
[ Table 7.1 from the textbook ]

36. Operations performed by this processor
Function Performed
Load Rx, Data
Rx  Data
Move Rx, Ry
Rx  [Ry]
Add Rx, Ry
Rx  [Rx] + [Ry]
Sub Rx, Ry
Rx  [Rx] - [Ry]
Where Rx and Ry can be one of four possible options: R0, R1, R2, and R3
[ Table 7.1 from the textbook ]

37. Operations performed by this processor
Function
Load 1
Move
Add
Sub
Rx1
Rx0
Register R0 1 R1 R2 R3
Ry1
Ry0
Register R0 1 R1 R2 R3

38. Operations performed by this processor
 Move R3, R0 f1 f0
Function
Load 1
Move
Add
Sub
Rx1
Rx0
Register R0 1 R1 R2 R3
Ry1
Ry0
Register R0 1 R1 R2 R3

39. Operations performed by this processor
 Add R1, R3 f1 f0
Function
Load 1
Move
Add
Sub
Rx1
Rx0
Register R0 1 R1 R2 R3
Ry1
Ry0
Register R0 1 R1 R2 R3

40. Operations performed by this processor
 Sub R0, R2 f1 f0
Function
Load 1
Move
Add
Sub
Rx1
Rx0
Register R0 1 R1 R2 R3
Ry1
Ry0
Register R0 1 R1 R2 R3

41. Operations performed by this processor
x x
 Load R2, Data f1 f0
Function
Load 1
Move
Add
Sub
Rx1
Rx0
Register R0 1 R1 R2 R3
Ry1
Ry0
Register R0 1 R1 R2 R3

42. Similar Encoding is Used by Modern Chips[

43. Sample Assembly Language Program For This Processor
Move R3, R0
Add R1, R3
Sub R0, R2
Load R2, Data

44. Machine Language vs Assembly Language
Meaning / Interpretation
011100
100111
110010
001000
Move R3, R0
Add R1, R3
Sub R0, R2
Load R2, Data
R3  [R0]
R1  [R1] + [R3]
R0  [R0] – [R2]
R2  Data

45. Machine Language vs Assembly Language
Meaning / Interpretation
011100
100111
110010
001000
Move R3, R0
Add R1, R3
Sub R0, R2
Load R2, Data
R3  [R0]
R1  [R1] + [R3]
R0  [R0] – [R2]
R2  Data

46. Machine Language vs Assembly Language
Meaning / Interpretation
011100
100111
110010
001000
Move R3, R0
Add R1, R3
Sub R0, R2
Load R2, Data
R3  [R0]
R1  [R1] + [R3]
R0  [R0] – [R2]
R2  Data
For short, each line
can be expresses as a
hexadecimal number

47. Machine Language vs Assembly Language
Meaning / Interpretation 1C 27 32 08
Move R3, R0
Add R1, R3
Sub R0, R2
Load R2, Data
R3  [R0]
R1  [R1] + [R3]
R0  [R0] – [R2]
R2  Data

48. Intel 8086 [

49. Intel 8086
Memory Address [

50. Intel 8086
Machine
Language [

51. Intel 8086
Assembly
Language [

52. Intel 8086
Comments [

54. Control signals asserted in each time step
(Load): I0
Extern
Rin = X
Done
(Move): I1
Rin = X
Rout = Y
(Add): I2
Rout = X
Ain
Gin
AddSub = 0
Gout
(Sub): I3
AddSub = 1
[ Table 7.2 from the textbook ]

55. Control signals asserted in each time step
(Load): I0
Extern
Rin = X
Done
(Move): I1
Rin = X
Rout = Y
(Add): I2
Rout = X
Ain
Gin
AddSub = 0
Gout
(Sub): I3
AddSub = 1
1 clock cycle
3 clock cycles
[ Table 7.2 from the textbook ]

56. A part of the control circuit for the processor
Reset
Up-counter
Clear w En y 1 2 3 T
2-to-4 decoder Q
Clock
[ Figure 7.10 from the textbook ]

57. What are the components?
Reset
Up-counter
Clear w En y 1 2 3 T
2-to-4 decoder Q
Clock
[ Figure 7.10 from the textbook ]

58. 2-Bit Up-Counter T y 2-to-4 decoder w En Q Clock Up-counter Clear
Reset
Up-counter
Clear w En y 1 2 3 T
2-to-4 decoder Q
Clock
[ Figure 7.10 from the textbook ]

59. 2-bit Synchronous Up-CounterQ
Clock 1
Clear_n

60. 2-bit Synchronous Up-Counter with EnableQ
Clock
Enable
Clear_n

61. 2-to-4 Decoder with Enable Input
Reset
Up-counter
Clear w En y 1 2 3 T
2-to-4 decoder Q
Clock
[ Figure 7.10 from the textbook ]

62. 2-to-4 Decoder with an Enable Input
[ Figure 4.13c from the textbook ]

63. 2-to-4 Decoder with an Enable Input1
(always enabled in this example)
[ Figure 4.13c from the textbook ]

64. In Chapter 6 we looked at the following Register Swap Example

65. Register Swap Controller
[ Figure 6.10 from the textbook ]

66. Register Swap Controller
Design a Moore machine control circuit for swapping the contents of registers R1 and R2 by using R3 as a temporary.
[ Figure 6.10 from the textbook ]

67. If an output is not given, then assume that it is 0.
State Diagram D: R 3
out 1 = in
Done , w C: 2 B:
A: No Transfer
Reset
If an output is not given, then assume that it is 0.
[ Figure 6.11 from the textbook ]

68. Animated Register Swap

69. Animated Register Swap
0xFF
0x42
0xC9
These are the original values of the 8-bit registers

70. Animated Register Swap1
0xFF
0x42
0xC9
For clarity, only inputs that are equal to 1 will be shown.

71. Animated Register Swap1
0xFF 1
0x42 1
0xC9

72. Animated Register Swap1
0xFF 1
0x42
0x42 1
0xC9

73. Animated Register Swap1
0xFF 1
0x42 1
0x42

74. Animated Register Swap1 1
0xFF 1
0x42
0x42

75. Animated Register Swap1 1
0xFF 1
0x42
0xFF
0x42

76. Animated Register Swap1 1
0xFF 1
0xFF
0x42

77. Animated Register Swap1 1
0xFF
0xFF 1
0x42

78. Animated Register Swap1 1
0xFF
0xFF
0x42 1
0x42

79. Animated Register Swap1 1
0x42
0xFF 1
0x42

80. Animated Register Swap
0x42
0xFF 1
0x42

81. If an output is not given, then assume that it is 0.
State Diagram D: R 3
out 1 = in
Done , w C: 2 B:
A: No Transfer
Reset
If an output is not given, then assume that it is 0.
[ Figure 6.11 from the textbook ]

82. Encoding #1: A=00, B=01, C=10, D=11 (Uses Two Flip-Flops)

83. y1 y2 y1 y2 y1 y2 Present Next state state Outputs A 00 1 B 01 10 C 111 B 01 10 C 11 D
w = 0
w = 1
y2y1
Y2Y1
Y2Y1
R1out
R1in
R2out
R2in
R3out
R3in
Done

84. Encoding #3: A=0001, B=0010, C=0100, D=1000 (One-Hot Encoding – Uses Four Flip-Flops)

85. Let's Complete the Circuit Diagram
R1out = R2in = y3
R2out = R3in = y2
R1in = R3out = Done = y4 D Q Y 2 1 w
Clock y 3 4
Y1 = w y1 + y4
Y2 = w y1
Y3 = y2
Y4 = y3

86. Implementing the States with a Counter

87. Control signals asserted in each time step
(Load): I0
Extern
Rin = X
Done
(Move): I1
Rin = X
Rout = Y
(Add): I2
Rout = X
Ain
Gin
AddSub = 0
Gout
(Sub): I3
AddSub = 1
[ Table 7.2 from the textbook ]

88. Derivation of the Control Inputs
See pages 434- and 435 in the textbook

89. Arithmetic Logic Unit (ALU)

90. Arithmetic Logic Unit (ALU)
Arithmetic Logic Unit (ALU) computes arithmetic or logic functions
Example: A four-function ALU has two selection bits S1 S0
(also called OpCode) to specify the function
00 (ADD), 01 (SUB), 10 (AND), 11 (OR)
Then the following set up will work S1 S0
Function
ADD 1
SUB
AND OR 00 01 10 11
ADD A B
MUX A
SUB A B A L U
AND A B
Result
Result B OR A B
Symbol
S1 S0
S1 S0
(OpCode)

91. An Alternative Design of Four-Function ALU
The previous design is not very efficient as it uses an adder and a subtractor circuit
We can design an add/subtract unit as discussed earlier
Then we can design a logical unit (AND and OR) separately
Then select appropriate output as result
What are the control signals, Add/Sub, Select0, and Select1?
Add/Sub 1
ADD/SUB A B
MUX S1 S0
Function
ADD 1
SUB
AND OR
AND A B 1
MUX
Result OR A B
Select0
Select1

92. A Digital System that Implements a Simple Processor
For this ALU,
A+B if AddSub=1
A-B if AddSub=0
[ Figure 7.9 from the textbook ]

93. Examples of Some Famous Microprocessors

94. Intel's 4004 Chip [

95. Technical specifications
Maximum clock speed was 740 kHz
Instruction cycle time: 10.8 µs (8 clock cycles / instruction cycle)
Instruction execution time 1 or 2 instruction cycles (10.8 or 21.6 µs), to instructions per second
Built using 2,300 transistors [

96. Technical specifications
Separate program and data storage.
The 4004, with its need to keep pin count down, used a single multiplexed 4-bit bus for transferring:
12-bit addresses
8-bit instructions
4-bit data words
Instruction set contained 46 instructions (of which 41 were 8 bits wide and 5 were 16 bits wide)
Register set contained 16 registers of 4 bits each
Internal subroutine stack, 3 levels deep. [

97. [

98. [

99. Intel's 8086 Chip [

100. [

101. Simplified block diagram of
Intel 8088 (a variant of 8086);
1=main registers;
2=segment registers and IP;
3=address adder;
4=internal address bus;
5=instruction queue;
6=control unit (very simplified!);
7=bus interface;
8=internal databus;
9=ALU;
10/11/12=external address/
data/control bus. [

102. Questions?

103. THE END