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Day 31: November 26, 2012 Inductive Noise

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Presentation on theme: "Day 31: November 26, 2012 Inductive Noise"— Presentation transcript:

1 Day 31: November 26, 2012 Inductive Noise
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 31: November 26, 2012 Inductive Noise Penn ESE370 Fall DeHon

2 Today Inductive Responses Calculating L Where do inductances show up
Impact of inductance on digital circuits How address Penn ESE370 Fall DeHon

3 Response What happens here? Penn ESE370 Fall DeHon

4 LC Response V2 Penn ESE370 Fall DeHon

5 LC Response Penn ESE370 Fall DeHon

6 LC Response Penn ESE370 Fall DeHon

7 LC Response Penn ESE370 Fall DeHon

8 LC Response Penn ESE370 Fall DeHon

9 LC Response Penn ESE370 Fall DeHon

10 LC Response Penn ESE370 Fall DeHon

11 LC Response Penn ESE370 Fall DeHon

12 Response? Penn ESE370 Fall DeHon

13 RLC Response V2 Penn ESE370 Fall DeHon

14 RLC Response Penn ESE370 Fall DeHon

15 RLC Response Penn ESE370 Fall DeHon

16 Solving for w Penn ESE370 Fall DeHon

17 RLC Penn ESE370 Fall DeHon

18 RLC Penn ESE370 Fall DeHon

19 RLC For What happens? What else happens? Oscillation Decay
Penn ESE370 Fall DeHon

20 RLC Response (R=100) Penn ESE370 Fall DeHon

21 When Oscillate For what R does this particular circuit oscillate?
Penn ESE370 Fall DeHon

22 RLC Response Penn ESE370 Fall DeHon

23 Inductance of Wire Penn ESE370 Fall DeHon

24 Inductance: Wire over Ground Plane
Inductance per cm with h=3mil, w=5mil? Penn ESE370 Fall DeHon

25 Lwire C and L per unit length Penn ESE370 Fall DeHon

26 Chip Inductance Cwire = 0.16 pF (for the 1mm) Cwire = 0.16nF/m
Permeability m0≈ mSi02=12.6×10-7H/m Permitivity eox=3.5×10-11F/m Penn ESE370 Fall DeHon

27 On Chip Cwire = 0.16 pF (for the 1mm) Cwire = 0.16nF/m
Permeability m0≈ mSi02=12.6×10-7H/m Permitivity eox=3.5×10-11F/m 276 pH (for 1 mm) Penn ESE370 Fall DeHon

28 Comparisons 5mil trace on PCB Protoboard wires (0.6mm diameter)
About 7nH/cm On chip wire 0.28nH/mm = 2.8nH/cm Penn ESE370 Fall DeHon

29 Inductors Bond pads Chip leads Long wire runs Cables
Src: Penn ESE370 Fall DeHon

30 Where Arise Penn ESE370 Fall DeHon

31 Signal Path Penn ESE370 Fall DeHon

32 Power Ground Penn ESE370 Fall DeHon

33 Shared Power/Ground Example: 74x04
Penn ESE370 Fall DeHon

34 Estimate Req, Ceq for gates in parallel 250 gates switching at clock
R0 = 25K W C0 = 0.01 fF say 10C0=0.1fF for typical load 250 gates switching at clock Req = 100W Ceq=25fF Assume L=1nH Penn ESE370 Fall DeHon

35 Power Ground Penn ESE370 Fall DeHon

36 RLC Response Penn ESE370 Fall DeHon

37 Today’s Chips How many gates? Penn ESE370 Fall DeHon

38 Multiple Power/Ground Pins
Use many power/ground pins How many pins on a package? Divide switching gates by pins To get effective load on each pin Penn ESE370 Fall DeHon

39 How Improve Penn ESE370 Fall DeHon

40 Minimize the L Make wires short Use power and ground planes
Think of power plane as a very wide wire Impact on C and L? Penn ESE370 Fall DeHon

41 Add Good C’s Bypass Capacitors – inside the inductances On board
On package On chip Penn ESE370 Fall DeHon

42 Bypass Capacitor Example
Penn ESE370 Fall DeHon

43 Bypassed Supplies (@ transistor)
Penn ESE370 Fall DeHon

44 Bypassed Output Penn ESE370 Fall DeHon

45 Minimize Current Draw More Power/Ground Pins Slower rise/fall times
Spread out switching Penn ESE370 Fall DeHon

46 Idea Long wires are inductive Bypass capacitors help Avoid them
Especially on power supplies Bypass capacitors help Penn ESE370 Fall DeHon

47 Admin Wednesday Lecture Thursday: Project 2 due Friday in Lab
Lab instructions out Wednesday Penn ESE370 Fall DeHon


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