1. ESE 437: Sensors and Instrumentation
Introduction to Verilog

2. Hardware Description Language

3. Verilog HDL - Module

4. Verilog HDL - Module

5. Verilog HDL - Module

6. Verilog HDL - Module

7. Verilog HDL - Module

8. Verilog HDL - Constant

9. Verilog HDL – Parameters

10. Verilog HDL – Parameters

11. Non-blocking Assignments

12. Blocking Assignments

13. iClick Question
In the following example, what is the values of register D?
A) D=A
B) D=B
C) D=C

14. Verilog HDL – Operators

15. Verilog HDL – Operators

16. Verilog HDL – Operators

17. Verilog HDL – Operators

18. Verilog HDL – Operators

19. Verilog HDL – Assignments

20. Verilog Example Implement a circular shift
Bit_0 will get the value from bit_7
Bit_1 will get the value from bit_2
Bit_2 will get the value from bit_3…
module circular_shift (input_reg, output_reg,clk)
output [7:0] output_reg;
input [7:0] input_reg;
input clk;
clk)
output_reg[1:7] = input_reg[0:6];
output_reg[0] = inout_reg[7];
endmodule

21. Verilog Example Implement a circular shift
Bit_0 will get the value from bit_7
Bit_1 will get the value from bit_2
Bit_2 will get the value from bit_3…
module circular_shift (input_reg, output_reg,clk)
output [7:0] output_reg;
input [7:0] input_reg;
input clk;
clk)
output_reg = {input_reg[6:0], inout_reg[7]};
endmodule

22. Verilog HDL – Assignments

23. Verilog HDL – Always

24. Verilog HDL – Always

25. Are these examples correct?

26. Parallel load register

27. Verilog HDL – If Instruction

28. Verilog HDL Example

29. Verilog HDL – Case Instruction

30. Verilog HDL Example

31. Verilog HDL – Module Instantiation

32. Verilog HDL – Module Instantiation

33. Verilog HDL – Examples

34. Verilog HDL – Examples

35. Verilog HDL – Example

36. Verilog HDL – Example

37. Verilog HDL – Example

38. Verilog HDL – Example

39. Verilog HDL – Example
// state declarizations reg [3:0] state; localparam STATE_INIT = 3'd0; localparam STATE_TX = 3'd1; localparam STATE_RX = 3'd2; localparam STATE_CALC = 3'd3; localparam STATE_IDLE = 3'd4; (posedge clock) begin case(state) begin STATE_INIT : begin state <= STATE_TX; end STATE_TX : begin if (conditional) begin state <= STATE_RX; end else begin state <= STATE_TX; end end
STATE_RX : begin // do something else end STATE_CALC : begin // do something else end endcase end

40. Verilog HDL Example