1. Hierarchical Approaches to Test Generation and Fault Simulation
REASON Tutorial, MIXDES, Szczecin, Poland June 25, 2004
Hierarchical Approaches to Test Generation and Fault Simulation
Raimund Ubar
Tallinn Technical University
D&T Laboratory
Estonia

2. Abstract
How to improve the testing quality at increasing complexities of today's systems?
Two main trends: defect-oriented test and high-level modelling
Both are caused by the increasing complexities of systems based on deep-submicron technologies
The complexity problems in testing digital systems are handled by raising the abstraction levels from gate to register-transfer level (RTL) instruction set architecture (ISA) or behavioral levels
To handle defects in circuits implemented in deep-submicron technologies, new fault models and defect-oriented test methods should be used
Trends to high-level modelling and defect-orientation are opposite
As a promising compromise and solution is: to combine hierarchical approach with defect orientation
Decision Diagrams serve as a good tool for hierarchical modelling of defects in digital systems

3. Introduction to Digital Test
Outline
Introduction to Digital Test
How to improve test quality at increasing complexity of systems
High-level modelling and defect-orientation
Decision Diagrams - beyond BDDs
Hierarchical test generation
General concepts
Test generation for RT Level systems
Test generation for Microprocessors
Hierarchical fault simulation
Overview of tools developed at D&T Lab

4. Introduction: the Problem is Money?
Cost of quality
How to succeed?
Try too hard!
How to fail?
(From American Wisdom)
Cost
Cost of
testing
100%
Test coverage function
Cost of
the fault
Time
Conclusion:
“The problem of testing
can only be contained
not solved”
T.Williams
Quality
Optimum
test / quality 0%
100%

5. Digital case (“continuous”)
Introduction
Paradox 1:
Digital world is finite,
analog world is infinite.
However, the complexity problem
was introduced by Digital World
Paradox 2:
If I can show that the system works,
then it should be not faulty.
But, what does it mean: it works?
32-bit accumulator has 264 functions
which all should work.
So, you should test all the
264 functions !
All life is an experiment.
The more experiments you make,
the better
(American Wisdom)
Stimuli
Response
System Y X
Digital case (“continuous”) Y
Analog case (samples) X

6. Introduction: How Much to Test?
Paradox:
264 input patterns (!)
for 32-bit accumulator
will be not enough.
A short will change the circuit
into sequential one,
and you will need because of that
265 input patterns
Mathematicians counted that Intel 8080
needed for exhaustive testing 37 (!) years
Manufacturer did it by 10 seconds
Majority of functions will never activated
during the lifetime of the system
Time can be your best friend
or your worst enemy
(Ray Charles)
Y = F(x1, x2, x3)
Bridging fault
State q y x1 1
&
& x2 * x3 1
Y = F(x1, x2, x3,q)

7. Introduction: Hierarchy
Paradox:
To generate a test
for a block in a system,
the computer
needed
2 days and 2 nights
An engineer
did it by hand
with 15 minutes
So, why
computers?
The best place to start is
with a good title.
Then build
a song around it.
(Wisdom of country music)
Sea of gates
&
Sequence of 216 bits
16 bit
counter 1
System

8. How to improve test quality at increasing complexity of systems
Outline
Introduction to Digital Test
How to improve test quality at increasing complexity of systems
High-level modelling and defect-orientation
Decision Diagrams (beyond BDDs)
Hierarchical test generation
General concepts
Test generation for RT Level systems
Test generation for Microprocessors
Hierarchical fault simulation
Overview of tools developed at D&T Lab

9. Complexity vs. Quality Problems: New solutions:
Traditional low-level test generation and fault simulation methods and tools for digital systems have lost their importance because of the complexity reasons
Traditional Stuck-at Fault (SAF) model does not quarantee the quality for deep-submicron technologies
New solutions:
The complexity can be reduced by raising the abstraction levels from gate to RTL, ISA, and behavioral levels
But this moves us even more away from the real life of defects (!)
To handle adequately defects in deep-submicron technologies, new fault models and defect-oriented test generation methods should be used
But, this is increasing even more the complexity (!)
To get out from the deadlock, these two opposite trends should be combined into hierarchical approaches

10. Fault and defect modeling
Defects, errors and faults
An instance of an incorrect operation of the system being tested is referred to as an error
The causes of the observed errors may be design errors or physical faults - defects
Physical faults do not allow a direct mathematical treatment of testing and diagnosis
The solution is to deal with fault models
System
Defect
Component
Fault
Error

11. Transistor Level Faults
Stuck-at-1
Broken (change of the function)
Bridging
Stuck-open  New State
Stuck-on (change of the function)
Short (change of the function)
Stuck-off (change of the function)
Stuck-at-0
SAF-model is not able to cover all the transistor level defects
How to model transistor defects ?

12. Mapping Transistor Faults to Logic Level
A transistor fault causes a change in a logic function not representable by SAF model
Function: y
Faulty function: x1 x4
Short
0 – defect d is missing
1 – defect d is present
d =
Defect variable: x2
Generic function with defect: x3 x5
Mapping the physical defect onto the logic level by solving the equation:

13. Mapping Transistor Faults to Logic Level
Function:
Faulty function:
Generic function with defect: y x1 x4
Short
Test calculation by Boolean derivative: x2 x3 x5

14. Why Boolean Derivatives?
Given:
Distinguishing function:
BD-based approach:
Using
the properties
of BDs,
the procedure of solving
the equation becomes easier

15. Functional Fault vs. Stuck-at Fault
Full 100% Stuck-at-Fault-Test is not able to detect the short:  No
Full SAF-Test
Test for the defect x1 x2 x3 x4 x5 1 - 2 3 4 5
Functional fault
The full SAF test
is not covering any of the patterns
able to detect
the given transistor defect

16. Defect coverage for 100% Stuck-at Test
Results:
the difference between stuck-at fault and physical defect coverages reduces when the complexity of the circuit increases (C2 is more complex than C1)
the difference between stuck-at fault and physical defect coverages is higher when the defect probabilities are taken into account compared to the traditional method where all faults are assumed to have the same probability

17. Generalization: Functional Fault Model
Constraints calculation:
Fault-free
Faulty
d = 1, if the defect is present
Component with defect:
Constraints:
Component F(x1,x2,…,xn) y Wd
Defect
Fault model:
(dy,Wd), (dy,{Wkd})
Logical constraints

18. Functional Fault Model Examples
Constraints:
Component with defect:
Component F(x1,x2,…,xn) y Wd
Constraints examples:
Defect
Logical constraints
FF model:
(dy,Wd), (dy,{Wkd})

19. Functional Fault Model for Stuck-ONx1 x2 y yd 1
Z: VY
NOR gate
Stuck-on
VDD x1 x2 RN Y x1 x2 RP
VSS
Condition of the fault potential detecting:
Conducting path for “10”

20. Functional Fault Model for Stuck-Open
NOR gate
Test sequence is needed: 00,10 x1 x2 y yd 1 Y’
Stuck-off (open)
t x1 x2 y
VDD x1 x2 Y x1 x2
VSS
No conducting path
from VDD to VSS for “10”

21. Functional Fault Modelxk
x*k
Example:
Bridging fault between leads xk and xl
The condition means that
in order to detect the short between leads xk and xl
on the lead xk
we have to assign to xk the value 1 and to xl the value 0. d xl
xk*= f(xk,xl,d)
Wired-AND model

22. Functional Fault Model
Example:
Bridging fault causes a feedback loop:
A short between leads xk and xl changes the combinational circuit into sequential one x1
& y x2
& x3
Equivalent faulty circuit: x1
& y
& x2
t x1 x2 x3 y x3
Sequential constraints:
&

23. First Step to Quality
How to improve the test quality at the increasing complexity of systems?
First step to solution:
Functional fault model
was introduced
as a means
for mapping physical defects
from the transistor or layout level
to the logic level
Component Low level k
WFk
WSk
Environment
Bridging fault
Mapping
High level
System

24. Outline High-level modelling and defect-orientation
Introduction to Digital Test
How to improve test quality at increasing complexity of systems
High-level modelling and defect-orientation
Decision Diagrams (beyond BDDs)
Hierarchical test generation
General concepts
Test generation for RT Level systems
Test generation for Microprocessors
Hierarchical fault simulation
Overview of tools developed at D&T Lab

25. Register Level Fault Models
RTL statement:
K: (If T,C) RD  F(RS1, RS2, … RSm),  N
Components (variables)
of the statement:
RT level faults:
K  K’ - label faults
T  T’ - timing faults
C  C’ - logical condition faults
RD  RD - register decoding faults
RS  RS - data storage faults
F  F’ - operation decoding faults
 - data transfer faults
 N - control faults
(F)  (F)’ - data manipulation faults
K - label
T - timing condition
C - logical condition
RD - destination register
RS - source register
F - operation (microoperation)
 - data transfer
 N - jump to the next statement

26. Fault Models for High-Level Components
Decoder:
- instead of correct line, incorrect is activated
- in addition to correct line, additional line is activated
- no lines are activated
Multiplexer (n inputs log2 n control lines):
- stuck-at - 0 (1) on inputs
- another input (instead of, additional)
- value, followed by its complement
- value, followed by its complement on a line whose address differs in 1 bit
Memory fault models:
- one or more cells stuck-at - 0 (1)
- two or more cells coupled

27. Fault models and Tests
Dedicated functional fault model for multiplexer:
stuck-at-0 (1) on inputs,
another input (instead of, additional)
value, followed by its complement
value, followed by its complement on a line whose address differs in one bit
Functional fault model
Test description

28. Faults and Test Generation Hierarchy
Functional
Structural
Higher Level Module
approach
approach ki
WFki
Component Lower level k F
Test W S k
WFk
System
WSki
Network
Bridging fault W F k
of modules
Environment F
Test W S k ki
Interpretation of WFk:
- as a test
on the lower level
- as a functional fault
on the higher level
Module
Network W F ki
of gates F
Test W d ki ki
Gat e
Circuit

29. Hierarchical Defect-Oriented Test Analysis
BDDs
DDs

30. Decision Diagrams (beyond BDDs)
Outline
Introduction to Digital Test
How to improve test quality at increasing complexity of systems
High-level modelling and defect-orientation
Decision Diagrams (beyond BDDs)
Hierarchical test generation
General concepts
Test generation for RT Level systems
Test generation for Microprocessors
Hierarchical fault simulation
Overview of tools developed at D&T Lab

31. Binary Decision Diagrams1 x1
Functional BDD 1 x2 x3
Simulation: x4 x5
Boolean derivative: x6 x7

32. Elementary Binary Decision Diagrams
Elementary BDDs:
AND x1 x1 x2 y x1 x2 x3
& x2 y x3 + x3
Adder x1 OR x2 y x1 1 y x1 x2 x3 x3 x2 x2 x3 x3
NOR x1 x2 y 1 x1 x2 x3 x3

33. Building a SSBDD for a Circuit
Structurally Synthesized BDDs:
DD-library: y a b
Given circuit: x1 a a x1 b
x22
x21 1 x2 y
&
x21 x3
x22 1 x3
Superposition of DDs 
SSBDD b y a
x22 y x1
x22
Compare to
Superposition of Boolean functions: x3
x21 x3 b a

34. Representing by SSBDD a Circuit
Structurally synthesized BDD
for a subcircuit (macro) 6 73 1 2 5 72 71 y
& 1 2 3 4 5 6 7 71 72 73 a b c d e y
Macro
To each node
of the SSBDD
a signal path in the circuit corresponds
y = cyey = cy  ey = x6,e,yx73,e,y  deybey
y = x6x73  ( x1  x2 x71) ( x5 x72)

35. Fault modeling on SSBDDs
The nodes represent signal paths through gates
Two possible faults of a DD-node represent all the stuck-at faults along the signal path
& 1 2 3 4 5 6 7 71 72 73 a b c d e y
Macro y 6 73 1 1 5 2 71 72 y
Test pattern:

36. High-Level Decision Diagrams
Superposition of High-Level DDs:
A single DD for a subcircuit 2 y # 4 1 R 2 M1 2 y y 3 1 R
+ R 1 2 R2 1
IN + R 2 1 IN 2 R 1 3 y 2 R
* R
R2 + M3 1 2 1
IN* R 2 M2
Instead of simulating
all the components in the circuit,
only a single path in the DD should be traced

37. High-Level Decision Diagrams
A digital system: A B C M
ADR
MUX 1 2 CC
CON D
Control Path
Data Path d / l FF y x q z
System is partitioned into 4 subcircuits, each represented by a DD

38. High-Level Vector Decision Diagrams
A system of 4 DDs
Vector DD A
M=A.B.C.q q
B’ + C’ C A q i B
+ C q x
A’ + B’ B i q 1 #1 x A  A
+ 1 #5 1 A 1 C 3 1 x i 
A’ + 1 A x q i  C’ C  C
+ B q #4 4 #3 x x A C A
+ B
+ C 1 B i
B’ + C’ A q x x
A’ + B’+C’ 1 1 #2 A C i B B q x B 2 A + C  B’ q 4 x  3 C #5 A B q q # 1 x
A’ + B’ C i B q 2 1 i  B’ #5 q C q x A
+ B x # B 4 1 A 1 A #5  3 1
B’ + C’ i 1 C x # 2 q C i  C’ 4 #5 q 4 1 2 x x # #5  C B 5 A 1
3,4 # 3

39. Fault Modeling on High Level DDs
High-level DDs (RT-level):
Terminal nodes represent:
RTL-statement faults:
data storage,
data transfer,
data manipulation faults
Nonterminal nodes represent:
RTL-statement faults:
label,
timing condition,
logical condition, register decoding,
operation decoding,
control faults

40. Hierarchical Diagnostic Modeling
High-Level DD-s
Two trends:
high-level modeling
to cope with complexity
low-level modeling
to cope with physical defects, to reach higher acuracy
Boolean differential algebra
BDD-s

41. Hierarchical test generation
Outline
Introduction to Digital Test
How to improve test quality at increasing complexity of systems
High-level modelling and defect-orientation
Decision Diagrams (beyond BDDs)
Hierarchical test generation
General concepts
Test generation for RT Level systems
Test generation for Microprocessors
Hierarchical fault simulation
Overview of tools developed at D&T Lab

42. Hierarchical Test Generation
In high-level symbolic test generation the test properties of components are often described in form of fault-propagation modes
These modes will usually contain:
a list of control signals such that the data on input lines is reproduced without logic transformation at the output lines - I-path, or
a list of control signals that provide one-to-one mapping between data inputs and data outputs - F-path
The I-paths and F-paths constitute connections for propagating test vectors from input ports (or any controllable points) to the inputs of the Module Under Test (MUT) and to propagate the test response to an output port (or any observable points)
In the hierarchical approach, top-down and bottom-up strategies can be distinguished

43. Hierarchical Test Generation Approaches
Bottom-up approach:
Top-down approach: A A
System
System a a’ B D B D’ C c C c’
a’,c’,D’
fixed
x - free
a,c,D
fixed
x - free a
a’x D
d’x
A = ax
D: B = bx
C = cx
A = a’x
D’ = d’x
C = c’x c
c’x
Module
Module

44. Hierarchical Test Generation Approaches
Bottom-up approach:
Pre-calculated tests for components generated on low-level will be assembled at a higher level
It fits well to the uniform hierarchical approach to test, which covers both component testing and communication network testing
However, the bottom-up algorithms ignore the incompleteness problem
The constraints imposed by other modules and/or the network structure may prevent the local test solutions from being assembled into a global test
The approach would work well only if the the corresponding testability demands were fulfilled A
System a B D C c
a,c,D
fixed
x - free a D
A = ax
D: B = bx
C = cx c
Module

45. Hierarchical Test Generation Approaches
Top-down approach: A
System
Top-down approach has been proposed to solve the test generation problem by deriving environmental constraints for low-level solutions.
This method is more flexible since it does not narrow the search for the global test solution to pregenerated patterns for the system modules
However the method is of little use when the system is still under development in a top-down fashion, or when “canned” local tests for modules or cores have to be applied a’ B D’ C c’
a’,c’,D’
fixed
x - free
a’x
d’x
A = a’x
D’ = d’x
C = c’x
c’x
Module

46. Hierarchical Test Generation on DDs
Hierarhical test generation with DDs: Scanning test (defect-oriented)
Single path activation in a single DD
Data function R1* R2 is tested
Decision Diagram y 4 3 1 R + 2 IN *
IN* #
Data path R 2 M 3 e + 1 a * b IN c d y 4
Test program:
Control: y1 y2 y3 y4 = x032
Data: For all specified pairs of (R1, R2)
Low level test data (constraints W)

47. Test Generation on High Level DDs
High-level test generation with DDs: Conformity test (High-level faults)
Decision Diagram
Multiple paths activation in a single DD
Control function y3 is tested R 2 y # 4
Data path 1 R R 2 M 3 e + 1 a * b IN c d y 4 2 2 y y 3 1 R + R 1 2 1 IN + R 2 1 IN 2 R 1 3 y 2 R * R 1 2 1
Control: For D = 0,1,2,3: y1 y2 y3 y4 = 00D2
Data: Solution of R1+ R2  IN  R1  R1* R2
IN* R
Test program: 2
Activating high-level faults:

48. Gate-level Test Generation
Structural gate-level testing:
Path activation
Fault sensitisation:
x7,1= D
Fault propagation:
x2 = 1, x1 = 1, b = 1, c = 1
Line justification:
x7= D = 0: x3 = 1, x4 = 1
b = 1: (already justified)
c = 1: (already justified) 1 1 1
Macro 1 1 d 2 a
&
& D 71 D D 1
& 3 e
& 7 72 1
& b 4 1 y D
& D 5 73
& c 1 6
Test pattern
Symbolic fault modeling:
D = if fault is missing
D = if fault is present

49. Defect-Oriented Test Generation
Test generation for a bridging fault:
Component F(x1,x2,…,xn) y
Activate
a path
Bridge between leads 73 and 6 Wd 1
Macro
Defect 1 1 d 2 a
& D 71
& D
Fault manifestation:
Wd = x6x7= 1: x6 = 0, x7 = 1,
x7 = D
Fault propagation:
x2 = 1, x1 = 1, b = 1, c = 1
Line justification:
b = 1: x5 = 0 D
& 3 e
& 7 72
& b 4 1 1 D y D 5
& 73
& c 1 6 Wd

50. Test Generation with SSBDDs
Defect Wd manifestation:
Wd = x6x7= 1: x6 = 0, x7 = 1, x7 = D Functional Fault dx7 propagation:
x1 = 1, x2 = 1, x5 = 0
& 1 2 3 4 5 6 7 71 72 73 a b c d e y
Macro y
(dx7,Wd) 6 73
No fault: dx7 =0: x7=1 1 1 5
Bridge between leads 7 and 6: (dx7,Wd) 2 71 72
Test pattern for the node at the constraint Wd = x6x7= 1:
Defect: dx7 =1: x7=0 y

51. Test Generation for RTL Digital Systems
High-level path activation on DDs
Transparency functions
on Decision Diagrams:
Y = C  y3 = 2, R3’ = 0
C - to be tested
R1 = B  y1 = 2, R3’ = 0
R1 - to be justified
Y,R y # R y # 3 3 2 2 1 1 R’ R’ 2 3 2 2 C R’ A 2 3 R’ C
2R’ 2 2
C+R’ C A # 2 1 A B C Y y 2 3 1 s R’ 1 1 R y 1 1 # # 1 1 R 2 R’ R’ 2 1 1 R’ + R 3 R’ B 1 3 1 A * F * R 1
F(B,R’ ) A R’ 3 1

52. Test Generation for RTL Digital Systems
System model A B C Y y 2 3 1 s
Data path R 2
Y,R y # R y # 3 3 2 2 + R 3 1 1 R’ R’ 2 3 2 * 2 F R C R’ A 1 2 2 3 R’ C
2R’ 2 2
Control path
C+R’ C A # q’ #
1001
q y1 y2 y3
4200 1 2 R’ =0
#2120
#3021
4211
0112 3 4 2 1 R’ 1 1 R y 1 1 # # 1 1 R’ R’ 1 1 2 R’ R’ B 1 3 1 A *
F(B,R’ ) A R’ 3 1

53. Test Generation for RTL Digital Systems
High-level test generation for data-path (example):
Time: t
t-1
t-2
t-3
q’=4
q’=2
q’=1
q’=0 D1 D y =2 3 y
= 0 R’
= 0 y 2
= 0 2 2 R
= D D2 3 # # R’ =0 2
q’=2
Fault
propagation
q’=1 y =2
Test generation steps:
Fault manifestation
Fault-effect propagation
Constraints justification 1 y
= 0 C
= D 3 A
= D R’ =0 1 3 # A * R’ R’
= D 1 1 2 B
= D 2
Fault manifestation
Constraints justification

54. Test Generation for RTL Digital Systems
Test generation step:
Fault-effect propagation + R 3 2 * F 1 A B C Y y s D D
Time: t
t-1
t-2
t-3
q’=4
q’=2
q’=1
q’=0 y
= 2
Y,R y # 3 3 3 y
= 0 R’
= 0 y 2
= 0 2 2 1 R =D 3 R’ # # 2 3
q y1 y2 y3 R’
= 0 2
q’=2 C R’ 2
Fault
propagation
q’=1 q’ #
1001 y
= 2 1 1 R’ C 2 1 R’ =0
#2120 y 2
= 0 C =D 3 A =D R’
= 0 # 1 3
#3021
C+R’ # 2 2 #
4200 A * R’ R’ =D 1 1 2 B =D 2 3
Fault manifestation #
4211 4
Constraints justification #
0112

55. Test Generation for RTL Digital Systems
Test generation step:
Line justification
Time: t-1
Path activation procedures on DDs:
Y,R y # 3 3 y 2 A
2R’ # R 1 3 R’ 1
Time: t
t-1
t-2
t-3 R’ 2 3 C R’
q’=4
q’=2
q’=1
q’=0 2 R’ C 2 y =2 3 y
= 0 R’
= 0 y 2
= 0 2 2
C+R’ 2 R =D 3 # #
q y1 y2 y3 q’ #
1001 R’ =0 2
q’=2 1 1
Fault
propagation R’ =0
#2120
q’=1 2 y 1 R’ 3 B
F(B,R’ ) # R 2 y =2 1 #
#3021 y
= 0 2 C =D 3 #
4200 A =D R’ =0 1 3 # 3 #
4211 A * R’ R’ =D 1 1 2 B =D 2
Fault manifestation 4 #
0112
Constraints justification

56. Test Generation for RTL Digital Systems
High-level test generation example: + R 3 2 * F 1 A B C Y y s
Time: t
t-1
t-2
t-3
q’=4
q’=2
q’=1
q’=0 y =2 3 y
= 0 R’
= 0 y 2
= 0 2 2 R =D 3 # #
Symbolic test sequence: R’ =0 2
q’=2
Fault
propagation
q’=1 y =2 1 y
= 0 C =D 3 A =D R’ =0 1 3 # A * R’ R’ =D 1 1 2 B =D 2
Fault manifestation
Constraints justification

57. Test Generation for Microprocessors
High-Level DDs for a microprocessor (example):
Instruction
set:
DD-model of the
microprocessor:
1,6 A I IN
I1: MVI A,D A  IN
I2: MOV R,A R  A
I3: MOV M,R OUT  R
I4: MOV M,A OUT  A
I5: MOV R,M R  IN
I6: MOV A,M A  IN
I7: ADD R A  A + R
I8: ORA R A  A  R
I9: ANA R A  A  R
I10: CMA A,D A   A 3
2,3,4,5
OUT I R A 4 7
A + R A 8 2
A  R R I A 9 5
A  R IN 10
 A
1,3,4,6-10 R

58. Test Generation for Microprocessors
High-Level DD-based structure of the microprocessor (example):
DD-model of the
microprocessor:
1,6 A I IN IN 3 R
2,3,4,5
OUT I R A 4 7
A + R I A
OUT 8 2
A  R R I A 9 5
A  R A IN 10
 A
1,3,4,6-10 R

59. Test Generation for Microprocessors
Scanning test program for adder:
Instruction sequence T = I5 (R)I1 (A)I7 I4
for all needed pairs of (A,R)
DD-model of the
microprocessor:
1,6 A I IN 3 I4
2,3,4,5
OUT
OUT I R A 4 A I7 7
A + R A A I1 8 2 R
IN(2)
A  R R I A R I5 9
A  R 5
IN(1) IN 10
Time: t
t - 1
 A
t - 2
t - 3
1,3,4,6-10
Observation Test Load R

60. Test Generation for Microprocessors
Conformity test program for decoder:
Instruction sequence T = I5 I1 D I4
for all DI1 - I10 at given A,R,IN
DD-model of the
microprocessor:
1,6 A I IN 3
Data generation:
2,3,4,5
OUT I R A 4 7
A + R A 8 2
A  R R I A 9
A  R 5 IN 10
 A
1,3,4,6-10
Data IN,A,R are generated so that
the values of all functions were different R

61. Hierarchical fault simulation
Outline
Introduction to Digital Test
How to improve test quality at increasing complexity of systems
High-level modelling and defect-orientation
Decision Diagrams (beyond BDDs)
Hierarchical test generation
General concepts
Test generation for RT Level systems
Test generation for Microprocessors
Hierarchical fault simulation
Overview of tools developed at D&T Lab

62. Deductive Fault Simulation
Gate-level fault list propagation
Fault list calculation: 1 1 b
La = L4  L5
Lb = L1  L2
Lc = L3  La
Ly = Lb Lc
Ly = (L1  L2) - (L3  (L4  L5))
& 1 2 1
Library of formulas for gates 1 1 y 3
& c 4 1 5 a
La – faults causing
erroneous signal
on the node a
Ly – faults causing erroneous signal
on the output node y

63. Deductive Fault Simulation with DDs
Macro-level fault propagation:
Fault list propagated:
Ly = (L1  L2) - (L3  (L4  L5)) 1 1 b
& 1 2 1 1
Fault list calculation on the DD 1 y 3
&
Faults on the activated path: c 4
Ly = (L1  L2) 1 5 a
Activated faults
First order fault masking effect:
Ly = (L1  L2) - L3 y 1 2
Second order masking effect (tradeoff):
Masking faults 3 4
Ly = (L1  L2) - (L3  (L4  L5)) 5
There is a tradeoff possibility between the speed and accuracy When increasing the speed of simulation the results will be not accurate (pessimistic): less fault detected than in reality

64. Hierarchical fault simulation
Set of patterns
Set of patterns
with faults
With faults P; P (R
)…P
( R ) P; P (R
)…P
( R )
High-Level 1 1 m m 1 1 n n
component
R: Faults
P: Pattern
High-Level
component
P: First Pattern
High-Level
component
Set of patterns
with faults
Sequence P; P (R
)…P
( R ) 1 1 n n
System
of patterns

65. Hierarchical fault simulation

66. Hierarchical fault simulation
Definition of the complex pattern:
D = {P, (P1,R1), …, (Pk, Rk)}
P is the fault-free pattern (value)
Pi (i = 1,2, ..., k) are faulty patterns, caused by a set of faults Ri
All the faults simulated causing the same faulty pattern Pi are put together in one group Ri
R1- Rk are the propagated fault groups, causing, correspondingly, the faulty patterns P1- Pk

67. Fault Simulation with DD-s
Fault propagation through a complex RT-level component
Decision diagram A 1 q xA
B + C
A + 1 3 xC
A + C 4 A 2
A - 1
A + B B
Sub-system
for A C A q xA xc
Dq = {1, 0 (1,2,5), 4 (3,4)},
DxA = {0, 1 (3,5)},
DxC = {1, 0 (4,6)},
DA = {7, 3 (4,5,7), 4 (1,3,9), 8 (2,8)},
DB = {8, 3 (4,5), 4 (3,7), 6 (2,8)},
DC = {4, 1 (1,3,4), 2 (2,6), 5 (6,7)}.
New DA to be calculated

68. Fault Simulation with DD-s
Fault propagation through a complex RT-level component
1 (1,2,3,4,5)
0 (1,2,3,4,5) q’ x
A’+1 A 1
Dq = {1, 0 (1,2,5), 4 (3,4)},
DxA = {0, 1 (2,5)},
DxC = {1, 0 (3,4)},
DA = {7, 3 (3,4,5,7), 4 (1,9), 8 (2,8)},
DB = {8, 3 (4,5), 4 (3,7), 6 (2,8)},
DC = {4, 1 (1,3,4), 2 (2,6), 5 (6,7)}.
8 ( Æ )
0 (1,2,5)
9 (8)
B’+C’
5 (9) 2
4 (7) 3 8( Æ
) + 1(1) = 9(1)
6(2) + 2(2) = 8(2)
3(5) + 4( Æ
) = 7(5)
4 (3,4)
0 (4) 1 x
New complex vector for A:
DA = {8, 3(4), 4(3,7), 5(9), 7(5), 9(1,8)} x A C
1 (3)
0 (4) A’ A’
8(2)
This fault is masked
4(3)
3 .4)

69. Overview of tools developed at D&T Lab
Outline
Introduction to Digital Test
How to improve test quality at increasing complexity of systems
High-level modelling and defect-orientation
Decision Diagrams (beyond BDDs)
Hierarchical test generation
General concepts
Test generation for RT Level systems
Test generation for Microprocessors
Overview of tools developed at
D&T Lab

70. DECIDER: Hierarchical ATPGy 1 2 3 4
Logic Synthesis
Scripts
RTL Model
(VHDL) a R 1 M + 1
Design Compiler
(Synopsys Inc.) e
RTL DD
Synthesis M R b 3 2 FU
Library
(VHDL) FU
Library
(DDs) M * IN 2
Gate Level
Descriptions R 2 y # 4
SSBDD Synthesis 1 R 2 2 y y 3 1 R + R
SSBDD Models
of FUs
RTL DD
Model 1 2 1 IN + R 1 2 IN 2 3
Hierarchical ATPG
Modules or subcircuits are represented as word-level DD structures R 1 y 2 R * R 1 2
Test patterns 1
IN* R 2

71. ATPG: Experimental Results
Reference ATPGs:
HITEC - T.M. Nierman, J.H. Patel, EDAC, 1991
GATEST - E.M.Rudnick et al., DAC, 1994
TTU:
DET/RAND - hierarchical deterministic- random ATPG
GENETIC - gate-level ATPG based on genetic algorithms

72. TURBO-TESTER: Low-Level TPG Tools
Fault models:
Stuck-at-faults
Stuck-opens
Delay faults
Methods:
Single fault
Parallel
Deductive
Methods:
Deterministic
Random
Genetic
Levels:
Gate
Macro
Test Generation
Fault Simulation
Design
Fault Location
Test
BIST Simulation
Methods:
BILBO
CSTP
Store/Generate
Fault Table
Fault Diagnosis
Test Optimization

73. Conclusions
Physical defects can be formally mapped to the logical level by Boolean differential calculus
Functional fault model is a universal means for mapping test results from lower levels to higher levels, giving a formal basis for hierarchical approaches to test generation and fault simulation
Decision diagrams is a suitable tool which can be used successfully both, on the logic level, and also on higher register transfer or behavioral levels

74. References
S.Mourad, Y.Zorian. Principles of Testing Electronic Systems. J.Wiley & Sons, Inc. New York, 2000, 420 p.
M.L.Bushnell, V.D.Agrawal. Essentials of Electronic testing. Kluwer Acad. Publishers, 2000, 690 p.
M. Abramovici et. al. Digital Systems Testing & Testable Designs. Computer Science Press, 1995, 653 p.
S. Minato. Binary Decision Diagrams and Applications for VLSI CAD. Kluwer Academic Publishers, 1996, 141 p.
R.Ubar. Test Synthesis with Alternative Graphs. IEEE Design and Test of Computers. Spring, 1996, pp
J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. JETTA: Theory and Applications. Kluwer Academic Publishers. Vol. 16, No. 3, pp , 2000.
R.Ubar, W.Kuzmicz, W.Pleskacz, J.Raik. Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED’02, San Jose, California, March 26-28, 2001, pp
T.Cibáková, M.Fischerová, E.Gramatová, W.Kuzmicz, W.Pleskacz, J.Raik, R.Ubar. Hierarchical Test Generation with Real Defects Coverage. Pergamon Press. J. of Microelectronics Reliability, Vol. 42, 2002, pp

75. References European Projects: Special thanks to: Contact data:
EEMCN, FUTEG, ATSEC, SYTIC, VILAB, REASON, eVIKINGS II
Special thanks to:
EU project IST REASON
Cooperation partners: IISAS Bratislava, TU Warsaw
Colleagues: J.Raik, A.Jutman, E.Ivask, E.Orasson a.o. (TU Tallinn)
Contact data:
Tallinn Technical University
Computer Engineering Department
Address: Raja tee 15, Tallinn, Estonia
Tel.: , Fax: