1. CSE 370 – Winter 2002 - Sequential Logic - 1
Overview
Last lecture
End of combinational logic
Very fast introduction to Verilog
Today
Sequential logic
Latches
12/5/2018
CSE 370 – Winter Sequential Logic - 1

2. Why do we study sequential logic
Why not only combinational logic?
We can build complex circuits: adder, multiplier etc.
But… real-world problems are sequential in time
We want to build systems that step through computations
These systems have memory and feedback
They use sequence of inputs to transition from state to state
12/5/2018
CSE 370 – Winter Sequential Logic - 2

3. Recall: Combinational vs. sequential systems
A simple model of a digital system is a unit with inputs and outputs:
Combinational systems are "memory-less"
The outputs depend only on the present inputs
Sequential systems have memory
The output values depend on the input values and previous input values
inputs
system
outputs
outputs
inputs
12/5/2018
CSE 370 – Winter Sequential Logic - 3

4. Recall: The steady-state abstraction
Combinational logic: Output depends on current inputs
After sufficient time has elapsed
Sequential logic: outputs retain their settled values
even after waiting for the transient activity to finish
Sequential logic relies on the steady-state abstraction:
the memory of a system is its state
changes in system state are only allowed to occur at specific times most often controlled by an external periodic clock
the clock period is the time that elapses between state changes. It must be sufficiently long so that the system reaches a steady-state before the next state change at the end of the period
12/5/2018
CSE 370 – Winter Sequential Logic - 4

5. Overview: Sequential logic
Assumes steady-state signals
Has memory
Usually employs feedback
Is clocked (or self-timed)
The basic devices and concepts
Latches, flip-flops, shift registers, state machines
Timing is critical
Asynchronous inputs must be synchronized
Metastability
12/5/2018
CSE 370 – Winter Sequential Logic - 5

6. CSE 370 – Winter 2002 - Sequential Logic - 6
Sequential circuits
Circuits with feedback
outputs = f(inputs, past inputs, past outputs)
basis for building "memory" into logic circuits
door combination lock is an example of a sequential circuit
If there is an error the lock doesn't open
Punch in 3 values in sequence and the door opens
new
equal
reset
value C1 C2 C3
mux control
multiplexer
comb. logic
comparator
state
clock
equal
open/closed
12/5/2018
CSE 370 – Winter Sequential Logic - 6

7. Memory in sequential circuits
Memory: Stored combination, present digit, errors or successes in past inputs
new
equal
reset
value C1 C2 C3
mux control
multiplexer
controller
clock
comparator
equal
open/closed
12/5/2018
CSE 370 – Winter Sequential Logic - 7

8. Feedback in sequential circuits
Inputs: Sequence of number values, reset
Outputs: Door open/close
Feedback: Comparator output ("equal" signal)
new
equal
reset
value C1 C2 C3
mux control
multiplexer
controller
clock
comparator
equal
open/closed
12/5/2018
CSE 370 – Winter Sequential Logic - 8

9. Clocking sequential circuits
Inputs are synchronized by the clock
Inputs are accepted when the clock signal goes high
Controller is clocked
Mux-control and open/closed signals change on the clock edge
new
equal
reset
value C1 C2 C3
mux control
multiplexer
controller
clock
comparator
equal
open/closed
12/5/2018
CSE 370 – Winter Sequential Logic - 9

10. CSE 370 – Winter 2002 - Sequential Logic - 10
What we will study
1) Tools and devices
Feedback, memory, state diagrams, clocking, timing
Latches, flip-flops, registers
2) Sequential circuit design
Counters, shift registers
The design process: From state diagrams to logic devices
Finite state machines (FSMs)
3) Implementation details
FSM optimization and state assignment
Detailed design examples
12/5/2018
CSE 370 – Winter Sequential Logic - 10

11. Circuits with feedback
How to control feedback?
what stops values from cycling around endlessly
X1 X2 • • • Xn
Z1 Z2 • • • Zn
switching network
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CSE 370 – Winter Sequential Logic - 11

12. Simplest circuits with feedback
Two inverters form a static memory cell
will hold value as long as it has power applied
How to get a new value into the memory cell?
selectively break feedback path
load new value into cell
"0"
"1"
"stored value"
"remember"
"load"
"data"
"stored value"
12/5/2018
CSE 370 – Winter Sequential Logic - 12

13. Memory with cross-coupled gates
Cross-coupled NOR gates (allows info to be changed)
similar to inverter pair, with capability to force output to 0 (reset=1) or 1 (set=1)
Cross-coupled NAND gates
similar to inverter pair, with capability to force output to 0 (reset=0) or 1 (set=0) R S Q Q' R S Q Q Q' S' R' R' S' Q
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CSE 370 – Winter Sequential Logic - 13

14. Timing behavior: the R-S latchQ Q'
Reset
Hold
Set
Reset
Set
Race
100 R S Q \Q
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CSE 370 – Winter Sequential Logic - 14

15. CSE 370 – Winter 2002 - Sequential Logic - 15
State diagrams
How do we characterize logic circuits?
Combinational: Truth tables
Sequential: State diagrams
Begin by drawing the states
States  possible values for fed back signals (Q, Q')
Example: R-S latch state diagram
Q Q' 0 1
Q Q' 1 0
Q Q' 0 0 R S Q Q'
Q Q' 1 1
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CSE 370 – Winter Sequential Logic - 15

16. State diagrams (con’t)
Now draw the state transitions
Transitions  Changes in state due to inputs
Example: R-S latch
Q Q' 0 1
Q Q' 1 0
Q Q' 0 0
Q Q' 1 1
SR=00
SR=11
SR=10
SR=01 R S Q Q'
possible oscillation between states 00 and 11
12/5/2018
CSE 370 – Winter Sequential Logic - 16

17. Observed R-S latch behavior
The 1-1 state is transitory
one of R or S usually changes first
Ambiguously returns to state 0-1 or 1-0
a so-called "race condition“ or non-deterministic transition
Q Q' 0 1
Q Q' 1 0
Q Q' 0 0
SR=10
SR=01
SR=00
SR=11
SR=00
12/5/2018
CSE 370 – Winter Sequential Logic - 17

18. R-S latch characteristic equation
Break feedback path R S Q Q'
S R Q(t) Q(t+) X X
hold
reset
set
not allowed
0 0
1 0
X 1
Q(t) R S
characteristic equation
Q(t+) = S + R’ Q(t)
12/5/2018
CSE 370 – Winter Sequential Logic - 18

19. CSE 370 – Winter 2002 - Sequential Logic - 19
Gating an R-S latch
Basic R-S latch is glitch sensitive
Static 0-hazards can cause state changes
Solution: Define when inputs can change
Use an enable input
Basic R-S latch
Gated R-S latch R S Q Q'
enable' S' Q' Q R' R S 
12/5/2018
CSE 370 – Winter Sequential Logic - 19

20. CSE 370 – Winter 2002 - Sequential Logic - 20
Gated R-S latch
Control when R and S inputs matter
State can only change when enable’ is a logic 0
enable' S' Q' Q R' R S
Set
Reset S' R'
enable' Q Q'
100
12/5/2018
CSE 370 – Winter Sequential Logic - 20

21. CSE 370 – Winter 2002 - Sequential Logic - 21
Clocks
Used to keep time
wait long enough for inputs (R' and S') to settle
then allow to have effect on value stored
Clocks are regular periodic signals
period (time between ticks)
duty-cycle (time clock is high between ticks - expressed as % of period)
duty cycle (in this case, 50%)
period
12/5/2018
CSE 370 – Winter Sequential Logic - 21

22. Using a clock as a gating signal
Controlling an R-S latch with a clock
can't let R and S change while clock is active (allowing R and S to pass)
only have half of clock period for signal changes to propagate
signals must be stable for the other half of clock period
clock' S' Q' Q R' R S
clock
R' and S'
changing
stable
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CSE 370 – Winter Sequential Logic - 22