1. EE207: Digital Systems I, Semester I 2003/2004
CSE221: Logic Design, Spring 2003
5-Dec-18
EE207: Digital Systems I, Semester I 2003/2004
CHAPTER 3-v:
Combinational Logic Design
(Section )
Chapter 3-v: Combinational Logic Design (Sections )

2. Chapter 3-v: Combinational Logic Design (3.9-3.11)
Overview
Binary Subtraction
2’’s complement
Extension to r’s complement
Subtraction with complements
Binary Adders/Subtractors
Signed numbers
Signed Addition/Subtraction
Overflow problem
Binary Multipliers
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Chapter 3-v: Combinational Logic Design ( )

3. Chapter 3-v: Combinational Logic Design (3.9-3.11)
Binary Subtraction
Unsigned numbers: minus sign is not explicitly represented.
Given 2 binary numbers M and N, find M-N:
Case I: M ≥ N, thus, MSB of Borrow is B M N Result is Correct Dif
Case II: N > M, thus MSB of Borrow is B M N Result requires correction! Dif
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4. Binary Subtraction (cont.)
In general, if N > M, Dif = M-N+2n, where n = # bits.
In Case II of the previous example, Dif= = 21.
To correct the magnitude of Dif, which should be N-M, calculate 2n-(M-N+2n).
This is known as the 2’’s complement of Dif.
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Chapter 3-v: Combinational Logic Design ( )

5. Chapter 3-v: Combinational Logic Design (3.9-3.11)
General Procedure
To subtract two n-bit numbers, M-N, in base 2:
Find M-N.
If MSB of Borrow is 0, then M ≥ N. Result is positive and correct.
If MSB of Borrow is 1, then N > M. Result is negative and its magnitude must be corrected by subtracting it from 2n (find its 2’s complement).
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6. Another Subtraction Example
Given M = and N = , find M-N B M N Dif n Dif
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7. Block Diagram for Subtractor
M0M1M2M3
N0N1N2N3 B
4-bit Subtractor
Enabled when B=1; otherwise, just pass the result from the subtractor
Selective 2’s Complementer
Not the best way to implement a subtractor circuit!
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Chapter 3-v: Combinational Logic Design ( )

8. Block Diagram for Binary Adder-Subtractor
M0M1M2M3
4-bit Subtractor
Selective 2’s Complementer B
N0N1N2N3 
Binary Adder
Quadruple 2-to-1 MUX
Result
Sub/Add
Sub/Add=1  Result=|M-N|
Sub/Add=0  Result=M+N
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Chapter 3-v: Combinational Logic Design ( )

9. Chapter 3-v: Combinational Logic Design (3.9-3.11)
Complements
There are 2 types of complements for each base-r system:
Radix (r’s) complement, ex. 2’s complement and 10’s complement.
Diminished radix (r-1’s) complement, ex. 1’s complement and 9’s complement.
We examine only 2’s and 1’s complements for base 2. Same concepts hole for other bases (ex. decimal).
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Chapter 3-v: Combinational Logic Design ( )

10. Chapter 3-v: Combinational Logic Design (3.9-3.11)
2’s Complement
For a positive n digit number N2 in binary, the 2's complement, 2C(N2), is given by:
2C(N2) = 2n-N2 , if n > , if n = 0
Example: N2 =1010
2C(N2) = 24-N2 = – = 01102
Example: N2 =11111
2C(N2) = 25-N2 = – = {
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Chapter 3-v: Combinational Logic Design ( )

11. Chapter 3-v: Combinational Logic Design (3.9-3.11)
2’s Complement (cont.)
Here’s an easier way to compute the 2’s complement:
Leave all least significant 0’s and first 1 unchanged.
Replace 0 with 1 and 1 with 0 in all remaining higher significant bits.
Examples:
N = N =
2’s complement ’s complement
complement
unchanged
complement
unchanged
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Chapter 3-v: Combinational Logic Design ( )

12. Chapter 3-v: Combinational Logic Design (3.9-3.11)
1’s Complement
For a positive n digit number N2 in binary, the 1's complement, 1C(N2), is given by:
1C(N2) = (2n-1) - N2
Example: N2 =011
1C(N2) = (23-1)-N2 = 1112 – 0112 = 1002
Example: N2 =1010
1C(N2) = (24-1) - N2 = – =
Observation: 1’s complement can be derived by just complementing all the bits in the number.
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Chapter 3-v: Combinational Logic Design ( )

13. Chapter 3-v: Combinational Logic Design (3.9-3.11)
Observation
Compare 1’s complement with 2’s complement:
2n-N = [(2n-1) - N] + 1
Thus, the 2’s complement can be obtained by deriving the 1’s complement and adding 1 to it.
Example:
N = 1001
2C(N) = 24 – N = – 1001 = 0111
1C(N) = 24 – 1 - N = 1111 – 1001 = 0110
 2C(N) = 1C(N) + 1 = = 0111
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Chapter 3-v: Combinational Logic Design ( )

14. Subtraction with Complements
To perform M-N = M+(-N), we may use a complement form to represent the negative number -N, and perform a “plain old addition”.
Need to be able to “convert” the result.
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Chapter 3-v: Combinational Logic Design ( )

15. Subtraction with 2’s complement
If we use 2's complements to represent negative numbers:
Form RI = M + 2C(N2) = M + (2n-N) = M – N + 2n.
If there is a nonzero carry out of the addition, M ≥ N, so discard that carry and the remaining digits are the result R = M-N.
Otherwise, M < N, so take the 2’s complement of RI (=2n- RI = 2n- (M – N + 2n) = N – M), and attach a minus sign in front, i.e., the result R is -2C([RI]2) = -(N-M).
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Chapter 3-v: Combinational Logic Design ( )

16. Chapter 3-v: Combinational Logic Design (3.9-3.11)
Example
A = (8410), B = (6710)
Find R = A-B:
2C(B) = (6110)
A+B = =
Discard carry, R = (1710) ✔
Find R = B-A:
2C(A) = (4410)
B+A = =
R = -2C(B+A) = (-17) ✔
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Chapter 3-v: Combinational Logic Design ( )

17. Subtraction with 1’s complement
If we use 1's complements to represent negative numbers:
Form RI = M + 1C(N2) = M + (2n-1-N) = M – N + 2n-1.
If there is a nonzero carry out of the addition, M ≥ N, so discard that carry and add 1 to the remaining digits. The result R = M-N.
Otherwise, M < N, so take the 1’s complement of RI (=2n- 1 - RI = 2 n- 1 - (M – N + 2n-1) = N – M ), and attach a minus sign in front, i.e., the result R is -1C([RI]2) = -(N-M).
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Chapter 3-v: Combinational Logic Design ( )

18. Chapter 3-v: Combinational Logic Design (3.9-3.11)
Example
A = (8410), B = (6710)
Find R = A-B:
1C(B) = (6010)
A+B = =
Discard carry and add 1, R = = (1710) ✔
Find R = B-A:
1C(A) =
B+A = =
R = -1C(B+A) = (-17) ✔
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Chapter 3-v: Combinational Logic Design ( )

19. Binary Adder/Subtractors
If we perform subtraction using complements, we eliminate the subtraction operation, and thus, can use an adder with appropriate complementer for subtraction.
Actually, we can use an adder for both addition and subtraction:
Complement subtrahend for subtraction
Do not complement subtrahend for addition
Thus, to form an adder-subtractor circuit, we only need a selective complementer and an adder.
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Chapter 3-v: Combinational Logic Design ( )

20. Binary Adder/Subtractors (cont.)
The subtraction A-B can be performed by taking the 2's complement of B and adding to A.
The 2's complement of B can be obtained by complementing B and adding one to the result. A-B = A + 2C(B) = A + 1C(B) = A + B’ + 1
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21. 4-bit Binary Adder/Subtractor
XOR gates act as programmable inverters
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Chapter 3-v: Combinational Logic Design ( )

22. 4-bit Binary Adder/Subtractor (cont.)
When S=0, the circuit performs A + B. The carry in is 0, and the XOR gates simply pass B untouched.
When S=1, the carry into the least significant bit (LSB) is 1, and B is complemented (1’s complement) prior to the addition; hence, the circuit adds to A the 1’s complement of B plus 1 (from the carry into the LSB).
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Chapter 3-v: Combinational Logic Design ( )

23. 4-bit Binary Adder/Subtractor (cont.)
S=0 selects addition
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24. 4-bit Binary Adder/Subtractor (cont.)1
S=1 selects subtraction
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25. 4-bit Binary Adder/Subtractor (cont.)
CSE221: Logic Design, Spring 2003
4-bit Binary Adder/Subtractor (cont.)
5-Dec-18
When C4 = 0 and S=1 it means that A < B and we must correct the result R3…R0 (see slide 15).
Thus, we must compute 2’s complement of R3…R0:
Use a specialized 2’s complement circuit or
Use the 4-bit Adder/Subtractor again, with A3…A0=0000, B3…B0=R3…R0, and S=1.
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Chapter 3-v: Combinational Logic Design ( )
Chapter 3-v: Combinational Logic Design (Sections )

26. Chapter 3-v: Combinational Logic Design (3.9-3.11)
Signed Binary Numbers
Signed-magnitude system: Singed numbers are represented using the MSB of the binary number to indicate the number’s sign:
If MSB is 0  number is positive
If MSB is 1  number is negative
Do not confuse with unsigned numbers!
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Chapter 3-v: Combinational Logic Design ( )

27. Signed Binary Numbers (cont.)
For example: is
in unsigned (- sign is implicit)
in singed (- sing is indicated in MSB=1)
Another example:
10112 is
1110 in unsigned
-310 in signed
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28. Signed Binary Numbers (cont.)
To implement signed-magnitude addition and subtraction we need to separate the sing bit from the magnitude bits, and treat the magnitude bits as an unsigned number (do correction whenever necessary).
To avoid correction, use the singed-complement system.
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29. Signed-Complement System
The magnitude of the negative number is represented in a complement form (2’s or 1’s complement).
Ex.: Use 8-bits to represent -910 and 910
-910 is:
in singed-magnitude
in singed-1’s complement
in singed-2’s complement
910 is in any of the above systems
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30. Signed-Magnitude Addition-Subtraction
To perform addition or subtraction of two numbers M and N in signed-magnitude, follow ordinary arithmetic rules:
Same signs: Add and keep same sign.
Different signs: Subtract N from M; if end Borrow is 1, correct result by taking its 2’s complement. Sign is negative.
Example: M: , N: N is negative, so find |M-N|= = , with end borrow 1. This implies that M-N is a negative number, so to correct find its 2’s complement Result is
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Chapter 3-v: Combinational Logic Design ( )

31. Signed-Complement Addition
“Addition of two signed numbers, with negative ones represented in signed-2’s complement, is obtained by adding the two numbers (including the sing bits). Carry out is discarded”.
Examples: (Assume 5-bit representations) (+10) (+10) (-10) (-10) (+5) (-5) (+5) (-5) (+15) (+5) (-5) (-15)
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Chapter 3-v: Combinational Logic Design ( )

32. Signed-Complement Addition (cont.)
Do not get confused reading negative numbers in signed-2’s complement! Remember, if MSB is 1 the number is negative and you need to find the 2’s complement of the magnitude.
Example: What’s the decimal equivalent of ?
Negative number, since MSB=1
Magnitude = ’s complement of magnitude =
The number is -5510
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Chapter 3-v: Combinational Logic Design ( )

33. Signed-Complement Subtraction
“Subtraction of two signed numbers, with negative ones represented in signed-2’s complement, is obtained by taking the 2’s complement of the subtrahend (including sing bit) and add it to the minuend. Discard carry out”.
Examples: (Assume 5-bit representations) (+10) (+10) (-10) (-10) (+5) (-5) (+5) (-5) (+10) (+10) (-10) (-10) (-5) (+5) (-5) (+5) (+5) (+15) (-15) (-5)
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Chapter 3-v: Combinational Logic Design ( )

34. Chapter 3-v: Combinational Logic Design (3.9-3.11)
The Overflow problem
If the sum of two n-bit numbers results in an n+1 number, then an overflow conditions is said to occur.
Detection of overflow can be implemented using either hardware or software.
Detection depends on number system used: signed or unsigned.
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Chapter 3-v: Combinational Logic Design ( )

35. The Overflow problem in Unsigned System
Addition:
When Carry out is 1.
Subtraction:
Can never occur. Magnitude of the result is always equal or smaller than the larger of the two numbers.
 Not REALLY a problem!
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Chapter 3-v: Combinational Logic Design ( )

36. The Overflow problem in Signed-2’s Complement
Remember that the MSB is the sign. But, the sign is also added! Thus, a carry out equal to 1 does not necessarily indicate overflow.
Overflow can occur ONLY when both numbers have the same sign. This condition can be detected when the carry out (Cn) is different than the carry at the previous position (Cn-1).
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Chapter 3-v: Combinational Logic Design ( )

37. The Overflow problem in Signed-2’s Complement (cont.)
Example 1: Let M=6510 and N=6510 in an 8-bit signed-2’s complement system.
M = N =
M+N = with Cn=0. This is clearly wrong! Bring Cn as the MSB to get (13010) which is correct, but requires 9-bits  overflow occurs.
Example 2: Let M=-6510 and N=-6510 in an 8-bit signed-2’s complement system.
M = N =
M+N = with Cn=1. This is wrong again! Bring Cn as the MSB to get (-13010) which is correct, but also requires 9-bits  overflow occurs.
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Chapter 3-v: Combinational Logic Design ( )

38. Overflow Detection in Signed-2’s Complement
Overflow conditions is detected by comparing the carry values into and out of the sign bit (Cn and Cn-1).
n-bit Adder/Subtractor with Overflow Detection Logic V
Cn+1 Cn C
n-bit Adder/Subtractor
C =1 indicates overflow condition when adding/subtr. unsigned numbers.
V=1 indicates overflow condition when adding/subtr. signed-2’s complement numbers
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Chapter 3-v: Combinational Logic Design ( )

39. Chapter 3-v: Combinational Logic Design (3.9-3.11)
Binary Multiplier
Binary multiplication resembles decimal multiplication:
n-bit multiplicand is multiplied by each bit of the m-bit multiplier, starting from LSB, to form n partial products.
Each successive set of partial products is shifted 1 bit to the left.
Derive result by addition the m rows of partial products.
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Chapter 3-v: Combinational Logic Design ( )

40. Binary Multiplier (cont.)
Example:
Multiplier A=A1A0 and multiplicand B=B1B0
Find C = AxB: B B x A A A0B1 A0B A1B1 A1B C C C C0
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Chapter 3-v: Combinational Logic Design ( )

41. Chapter 3-v: Combinational Logic Design (3.9-3.11)
Binary Multiplier Circuit 2-bit by 2-bit multiplier
Half Adders are Sufficient
since there is no Carry-in
in addition to the two inputs
to sum
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Chapter 3-v: Combinational Logic Design ( )

42. Chapter 3-v: Combinational Logic Design (3.9-3.11)
Binary Multiplier Circuit 4-bit by 3-bit multiplier
4 bit by 3 bit yields a
7 bit result
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Chapter 3-v: Combinational Logic Design ( )