1. Programmable Configurations
Read Only Memory (ROM) –
a fixed array of AND gates and a programmable array of OR gates
Programmable Array Logic (PAL)Ò –
a programmable array of AND gates feeding a fixed array of OR gates.
Programmable Logic Array (PLA) –
a programmable array of AND gates feeding a programmable array of OR gates.
Complex Programmable Logic Device (CPLD) /Field- Programmable Gate Array (FPGA) –
complex enough to be called “architectures”

2. ROM, PAL and PLA Configurations
Fixed
Programmable
Programmable
Inputs
AND array
Outputs
Connections
OR array
(decoder)
(a) Programmable read-only memory (PROM)
Programmable
Inputs
Programmable
Fixed
Outputs
Connections
AND array
OR array
(b) Programmable array logic (PAL) device
Programmable
Programmable
Programmable
Programmable
Inputs
Outputs
Connections
AND array
Connections
OR array
(c) Programmable logic array (PLA) device

3. Read Only Memory
Read Only Memories (ROM) or Programmable Read Only Memories (PROM) have:
N input lines,
M output lines, and
2N decoded minterms.
Fixed AND array with 2N outputs implementing all N-literal minterms.
Programmable OR Array with M outputs lines to form up to M sum of minterm expressions.
A program for a ROM or PROM is simply a multiple-output truth table
If a 1 entry, a connection is made to the corresponding minterm for the corresponding output
If a 0, no connection is made

4. Read Only Memory Example
Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines)
The fixed "AND" array is a “decoder” with 3 inputs and 8 outputs implementing minterms.
The programmable "OR“ array uses a single line to represent all inputs to an OR gate. An “X” in the array corresponds to attaching the minterm to the OR
Read Example: For input (A2,A1,A0) = 011, output is (F3,F2,F1,F0 ) = 0011.
What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)? D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 A B C F0 F1 F2 F3 X
F3 = D7 + D5 + D2 = A2 A0 + A2’ A1 A0’
F2 = D7 + D0 = A2 A1 A0 + A2’ A1’ A0’
F1 = D4 + D1 = A1 A1’ A0’ + A2’ A1’ A0
F0 = D7 + D5 + D1 = A2 A0 + A1’ A0

5. Programmable Array Logic (PAL)
The PAL is the opposite of the ROM, having a programmable set of ANDs combined with fixed ORs.
Disadvantage
ROM guaranteed to implement any M functions of N inputs. PAL may have too few inputs to the OR gates.
Advantages
For given internal complexity, a PAL can have larger N and M
Some PALs have outputs that can be complemented, adding POS functions
No multilevel circuit implementations in ROM (without external connections from output to input). PAL has outputs from OR terms as internal inputs to all AND terms, making implementation of multi-level circuits easier.

6. Programmable Array Logic Example9 1 2 3 4 5 6 7 8
AND gates inputs
Product
term 10 11 12 F I = C B A
4 = D X
4-input, 3-output PAL with fixed, 3-input OR terms
What are the equations for F1 through F4?
F1 = C’ + A’B’
F2 = A’BC’ + AC + AB’
F3 = AD + BD + F1
F4 = AB + CD + F1’
F3 = AD + BD + F1 = AD + BD + A’B+ C’ = AD + BD + A’B’ + C’
F4 = AB + CD + F1’ = AB + CD + (A’B’ + C’)’ = AB + CD + AC + BC

7. Programmable Logic Array (PLA)
Compared to a ROM and a PAL, a PLA is the most flexible having a programmable set of ANDs combined with a programmable set of ORs.
Advantages
A PLA can have large N and M permitting implementation of equations that are impractical for a ROM (because of the number of inputs, N, required 
A PLA has all of its product terms connectable to all outputs, overcoming the problem of the limited inputs to the PAL ORs
Some PLAs have outputs that can be complemented, adding POS functions
Disadvantage
Often, the product term count limits the application of a PLA. Two-level multiple-output optimization reduces the number of product terms in an implementation, helping to fit it into a PLA.

8. Programmable Logic Array Example
Fuse intact
Fuse blown 1 F 2 X A B C 3 4
A B
A C
B C
What are the equations for F1 and F2?
Could the PLA implement the functions without the XOR gates?
F1 = AB +BC + AC
F2 = (AB + A’B’)’ = (A’ + B’) (A + B) = A’B + AB’
No. If only SOP functions used, requires at least 5 AND gates.
3-input, 3-output PLA with 4 product terms

9. Combinational Functions and Circuits
Rudimentary logic functions
Decoding
Encoding
Selecting

10. Rudimentary Logic Functions
Functions of a single variable X
Can be used on the inputs to functional blocks to implement other than the block’s intended function 1 F =
(a) V CC
or V DD
(b) X
(c)
(d)

11. Multiple-bit Rudimentary Functions
Multi-bit Examples:
A wide line is used to represent a bus which is a vector signal
In (b) of the example, F = (F3, F2, F1, F0) is a bus.
The bus can be split into individual bits as shown in (b)
Sets of bits can be split from the bus as shown in (c) for bits 2 and 1 of F.
The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0 of F. A F A 3 2 3 1 F 1 2
2:1 4
F(2:1) 2 4 F F F 1 1
(c) A F A
(a)
(b) 3
3,1:0 4
F(3), F(1:0) F
(d)

12. Enabling Function
Enabling permits an input signal to pass through to an output
Disabling blocks an input signal from passing through to an output, replacing it with a fixed value
The value on the output when it is disable can be Hi-Z (as for three-state buffers and transmission gates), 0 , or 1
When disabled, 0 output
When disabled, 1 output

13. Decoders
Multiple-input multiple-output logic circuit which maps coded inputs to coded outputs
n input bits can code upto 2n different output bits
n-to-m decoder: maps n-bit input to m-bit output where m < 2n

14. Decoders General decoder structure Typically n inputs, 2n outputs
2-to-4, 3-to-8, 4-to-16, etc.

15. Binary 2-to-4 decoder
Note “x” (don’t care) notation.

16. 2-to-4-decoder logic diagram
m0=I1’I0’
m1=I1’I0
m2=I1I0’
m3=I1I0

17. Decoder Expansion
3-to-8 decoder out of 2 2-to-4 decoders with enable

18. Decoder and OR Gate Implementation of a Binary Adder
Arithmetic sum of three bits X,Y,Z
Output pair (C,S)
S(X,Y,Z) =
C(X,Y,Z) =

19. S(X,Y,Z) =
C(X,Y,Z) =

20. Decoder Applications Microprocessor memory systems
Selecting different banks of memory
Microprocessor input/output systems
Selecting different devices
Microprocessor instruction decoding
Enabling different functional units
Memory chips
Enabling different rows of memory depending on address
Lots of other applications
Seven segment decoder, 4-to-7 decoder

21. Encoders vs. Decoders
Decoder
Encoder

22. Binary encoders

23. Need priority in most applications

24. Priority Encoder

25. A0 = D3 + D1D2’
A1 = D2 + D3
V = D0 + D1 + D2 + D3

26. Another approach to the design of 8-input priority encoder

27. Priority-encoder logic equations

28. Selecting
Selecting of data or information is a critical function in digital systems and computers
Circuits that perform selecting have:
A set of information inputs from which the selection is made
A single output
A set of control lines for making the selection
Logic circuits that perform selecting are called multiplexers
Selecting can also be done by three-state logic or transmission gates

29. Multiplexers
MUX:
Selects binary information from one of many input lines and directs the information to a single output line.
Selection of a particular input is controlled by a set of input variables.
# of selection control bits: n
# of possible input lines: 2n
# of output: 1
2n-to-1 MUX

30. Multiplexers

31. 4-to-1-Line MUX

32. Quadruple 2-to-1-Line MUX

33. Combinational Circuit Implementation Using MUX
F(X,Y,Z)=m(1,2,6,7) using a 4-to-1 MUX

34. F(A,B,C,D)=m(1,3,4,11,12,13,14,15)

35. Demultiplexer Inverse of the MUX
Receives information from a single line and transmits it to one of the 2n possible output lines
1-to-4-Line DMUX / to-4-Line Decoder

36. Binary Adders Arithmetic circuits: Present a hierarchical design
combinational circuits with add, subt, mult & div.
Present a hierarchical design
Simple addition of two bits
0+0 = 02, 0+1 = 12, 1+0 = 12 and 1+1 = 102
Half Adder:
Combinational circuit that adds two bits
Full Adder:
Combinational circuit that adds three bits (two input, one carry)

37. Half Adder
Sum of two binary digits
S=X’Y+XY’
C=XY

38. Full Adder
Sum of three binary digits

39. Logic Diagram for Full Adder
XY Z XY
Z(XY)
XY + Z(XY)

40. Binary Ripple Carry Adder
The parallel adder of n binary full adders
Carry out  Carry in of next full adder

41. Carry Lookahead Adder Ripple carry adder Define a partial full adder
Simple but has a long circuit delay
Define a partial full adder
Try to lower gate delays for ripple carry adder

42. Binary Adder/Subtractor

43. Overflow When does it occur? How do we detect it? 01110 10000
+12 ? ? 10110

44. Binary Multipliers

45. 4-bit by 3-bit multiplier