1. Introduction to Programmable Logic Devices
Aleksandra Kovacevic
Veljko Milutinovic
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2. Introduction
Comparison of Standard Logic Circuits and Programmable Logic Circuits
Evolution and Overview of PLC:
PROM, PLA, PAL
CPLD
FPGA
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3. Standard Logic Circuits
Programmable Logic Circuits
Realize single function or set of functions, once defined and with no possibility of changing.
Contains great number of standard logic circuits
Possibility of realizing many various functions
Hardware can configure any time user need to only by programming.
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4. Standard Logic Circuits
Appropriate for many applications because of possibility of realization in mass production for relative low cost.
Standard logic circuits are sometimes the best choice in high-performance devices.
Disadvantage: Not permitting design updates (function changes) with no hardware replacement necessary.
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5. Field- Programmable Logic Devices
Component function is defined by users program.
Logic Cells Fields are interconnected by programming.
Advantages:
Flexible design that changes by reprogramming, ease of design changes
Reduce prototype-product time
Large scale integration (over gates)
Reliability increased, low financial risk
Smaller device, low start-up cost
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6. Programmable logic device
FPLDs Representatives
PLA - Programmable Logic Arrays
PAL - Programmable Array Logic
CPLD - Complex Programmable Logic Devices
FPGA - Field Programmable Gate Arrays
Programmable logic device
PLD
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7. Evolution of PLD: Why not PROM?
A special device (called a burner), used to put the information, supplies an electrical current to specific cells in the ROM that effectively blows a fuse in them = burning the PROM. From that point on, chip is read-only.
PROM was the first type of user-programmable chip; address lines = logic circuit inputs data lines = logic circuit outputs
PROMs are inefficient architecture for realizing logic circuit:
Logic functions rarely require more than few product terms
PROM contains a full decoder for its address inputs.
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8. Evolution of PLD: PLA Drawbacks:
PLA was the first device developed for implementing
Consist of two levels of logic gates - programmable “wired” AND-plane & OR-plane
Drawbacks:
Expensive to manufacture
Offered somewhat poor speed-performance
Note:
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9. Evolution of PLD: PAL™
Overcame weaknesses of PLA
Single level of programmability - consists of a programmable “wired” AND-plane & fixed OR-gates
Simpler to program and cheaper implementation
Limited numbers of terms in each output
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Note:
PAL is a trademark of Advanced Micro Devices

10. Evolution of PLD: Register PLA
Contain flip flops connected to the OR gate outputs
sequential circuits can be realized
Importance:
Profound effect on digital hardware design
Basis for more sophisticated architectures
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11. Evolution of PLD: CPLD
Programmable Interconnect Array
- Capable of connecting any LAB input or output to any other LAB
possibility to produce devices with higher capacity than SPLDs.
Technology advanced
Structure grows too quickly in size as the number of inputs is increased
Integrating multiple SPLDs onto a single chip - the only feasible way to provide large capacity devices based on SPLD
Programmably connect the SPLD blocks together
Logic capacity up to the equivalent of about 50 typical SPLD devices
Logic Array Blocks
- Complex SPLD-like structure
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12. ... and finally...
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13. contains a set of basic functions (gates, FFs, memory cells)
Evolution of PLD: FPGA
contains a set of basic functions (gates, FFs, memory cells)
Difficult extending CPLDs architectures to higher densities - a different approach is needed
FPGAs comprise an array of uncommited circuit elements, called logic blocks, and interconnect resources
FPGA configuration is performed through programming by the end user.
Xilinx FPGA Configuration
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14. Introduction to Programmable Logic Devices
Aleksandra Kovacevic
Veljko Milutinovic
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