1. Testing for Faults, Looking for Defects
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
IEEE Latin American Test Workshop, March 2011 Keynote
NYUAD Seminar, April 2011, Invited Talk
March 28/April 15, 2011
Testing for Faults, Looking for Defects

2. VLSI Chip Yield
A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process.
A chip with no manufacturing defect is called a good chip.
Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y.
Cost of a chip:
Cost of fabricating and testing a wafer

Yield × Number of chip sites on the wafer
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3. Clustered VLSI Defects
Good chips
Faulty chips
Defects
Wafer
Unclustered defects
Wafer yield = 12/22 = 0.55
Clustered defects (VLSI)
Wafer yield = 17/22 = 0.77
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4. Testing for Faults, Looking for Defects
Yield Parameters
Defect density (d ) = Average number of defects per unit of chip area
Chip area (A )
Clustering parameter (a)
Negative binomial distribution of defects, p (x ) = Prob(number of defects on a chip = x )
Γ (α +x ) (Ad / α) x
=  . 
x ! Γ (α) (1+Ad / α) α+x
where Γ is the gamma function
α = 0, p (x ) is a delta function (max. clustering)
α =  , p (x ) is Poisson distr. (no clustering, William/Brown)
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5. Testing for Faults, Looking for Defects
Yield Equation
Y = Prob( zero defect on a chip ) = p (0)
Y = ( 1 + Ad / α ) – α
Example: Ad = 1.0, α = 0.5, Y = 0.58
Unclustered defects: α = 
, Y = e – Ad
Example: Ad = 1.0, α = , Y = 0.37
too pessimistic !
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6. Defect Level or Reject Ratio
Defect level (DL) is the ratio of faulty chips among the chips that pass tests.
DL is measured as defective parts per million (dpm, or simply ppm).
DL is a measure of the effectiveness of tests.
DL is a quantitative measure of the manufactured product quality:
For commercial VLSI chips a DL higher than 500 dpm is considered unacceptable.
Chip manufacturers strive for much lower defect levels. Below 100 dpm means high quality.
Zero-defect refers to 3.4 dpm or below.
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7. Testing for Faults, Looking for Defects
Determination of DL
From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL.
From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL.
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8. Modified Yield Equation
Three parameters:
Fault density, f = average number of stuck-at faults per unit chip area
Fault clustering parameter, b
Stuck-at fault coverage, T
The modified yield equation:
Y (T ) = (1 + TAf / β) – β
Assuming that tests with 100% fault coverage
(T =1.0) remove all faulty chips,
Y = Y (1) = (1 + Af / β) – β
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9. Testing for Faults, Looking for Defects
Defect Level
Y (T ) - Y (1)
DL (T ) = 
Y (T )
( β + TAf ) β
= 1 – 
( β + Af ) β
Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A, β is the fault clustering parameter. Af and β are determined by test data analysis.
b = 
, Y (T ) = e –TAf and DL(T ) = 1 – Y (1)1 –T
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10. Example: SEMATECH Chip
Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont
116,000 equivalent (2-input NAND) gates
304-pin package, 249 I/O
Clock: 40MHz, some parts 50MHz
0.8m CMOS, 3.3V, 9.4mm x 8.8mm area
Full scan, 99.79% fault coverage
Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock
Data obtained courtesy of Phil Nigh (IBM)
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11. Test Coverage from Fault Simulator
Stuck-at fault coverage
Vector number, V
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12. Testing for Faults, Looking for Defects
Measured Chip Fallout
Measured chip fallout, 1 – Y(d )
Vector number, V
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13. Testing for Faults, Looking for Defects
Model Fitting
Unclustered faults:
1 – e– TAf
Af = 0.31, β = 
Y (1) =
Clustered faults:
1 – (1+TAf/β)– β
Af = 2.1, β = 0.083
Chip fallout and computed 1-Y (T )
Y (1) =
Measured chip fallout
Stuck-at fault coverage, T
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14. Testing for Faults, Looking for Defects
Computed Defect Level
(1 – )×106
(1 – )×106
Unclustered
faults, β = 
Clustered
faults, β = 0.083
Defect level (dpm)
Stuck-at fault coverage (%)
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15. Testing for Faults, Looking for Defects
Reexamine Assumption
Assumption: 100% fault coverage leads to zero defect level.
Reality: 100% defect coverage leads to zero defect level.
Must examine the two coverages.
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16. Fault vs. Defect Coverage
Fault coverage, T(V ) Defect coverage, D(V )
Coverage = % of stuck-at faults detected by vectors.
Faults are countable.
Alternative definition: T (V ) = Prob (detection by V vectors | a fault is present)
All faults assumed equally probable on a faulty chip.
Determined theoretically.
Coverage = % of real defects detected by vectors.
Many types, large numbers.
Alternative definition: D (V ) = Prob (detection by V vectors | a defect is present)
Each defect may have a different probability of occurrence.
Determined experimentally.
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17. Testing for Faults, Looking for Defects
Defect Coverage
D (V ) = Prob (detection by V vectors | defect present)
Prob(detection by V vectors and defect present)
= 
Prob(defect present) or 1 – Y (d = 1)
1 – Y (d )
=  Y(d = 1) is true yield
1 – Y (d = 1)
Measured yield, Y (d ) and estimated true yield can provide a statistical estimate for defect coverage. Source of inaccuracy: true yield, Y(d = 1), is not known.
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18. Defect and Fault Coverages
Defect coverage D(V ) from test data
Y(d =1) =
Coverage
Fault coverage T(V ) from fault simulator
Vector number (V )
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19. Defect vs. Fault Coverage
Defect coverage, D
D > T
D < T
Fault coverage, T
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20. Testing for Faults, Looking for Defects
Conclusion
Defect coverage can be determined from the measured test data.
Assumption:
Either, tests are capable of activating the defect (Q: Can a delay defect be detected by slow-speed stuck-at fault tests?)
Or, the real defect is clustered with faults detectable by the tests.
The above assumption, “DL = 0 at f = 100%,” may be justified since fault coverage appears to be more pessimistic than defect coverage.
Defect coverage D (V ) is a transformation of test data:
Vector 0 → coverage 0%
Vector  → coverage 100%
Unclustered fault assumption adds pessimism.
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21. Testing for Faults, Looking for Defects
Future Directions
Defect density, d, should not be confused with defect coverage, D (V ):
d = number of defects per unit area
D (V ) = percentage of all possible defects detected by V vectors
Analyze test data for yield, defect coverage and defect level without involving modeled faults.
Experiment Y
Chip fallout fraction
Fraction of chips
Vectors, V
1.0
Prob(defect occurrence)
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Testing for Faults, Looking for Defects

22. Testing for Faults, Looking for Defects
Directions . . .
Diagnosis: Defects do not conform to any single fault model.
Question: Which is better?
100% coverage for one fault model, or
some coverage for multiple fault models
March 28/April 15, 2011
Testing for Faults, Looking for Defects

23. Testing for Faults, Looking for Defects
Directions . . .
Generate tests for defect coverage and diagnosis.
Question: which is better?
100% stuck-at fault coverage, or
100% diagnostic coverage of stuck-at faults, or
N-detect tests (longer tests), or
Any of the above + random vectors.
March 28/April 15, 2011
Testing for Faults, Looking for Defects

24. Testing for Faults, Looking for Defects
References
The clustered fault model used for Sematech data is described in the book: M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Chapter 3.
The unclustered defect model is from the paper: T. W. Williams and N. C. Brown, “Defect Level as a Function of Fault Coverage,” IEEE Trans. Computers, vol. C-30, no. 12, pp , Dec
The discussion on defect coverage is from a presentation: J. T. de Sousa and V. D. Agrawal, “An Experimental Study of Tester Yield and Defect Coverage,” IEEE International Test Synthesis Workshop, Santa Barbara, California, March 2001.
A direct analysis of defect level without involving the stuck-at fault coverage is given in the paper: S. C. Seth and V. D. Agrawal, “On the Probability of Fault Occurrence,” Defect and Fault Tolerance in VLSI Systems, I. Koren, editor, Plenum Publishing Corp., 1989, pp
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Testing for Faults, Looking for Defects