Synthesis of asynchronous controllers from Signal Transition Graphs:

Synthesis of asynchronous controllers from Signal Transition Graphs:
Jordi Cortadella Universitat Politècnica de Catalunya Joint work with: Michael Kishinevsky, Intel Corporation Alex Kondratyev, Xilinx Luciano Lavagno, Politecnico di Torino Alex Yakovlev, University of Newcastle EMICRO 2016 Synthesis of async controllers from STGs

Synthesis of async controllers from STGs
Outline Asynchronous controllers Specification with Signal Transition Graphs Synthesis from Signal Transition Graphs Petrify Advanced topics EMICRO 2016 Synthesis of async controllers from STGs

Synchronous circuit R CL R CL R CL R CLK Implicit synchronization EMICRO 2016 Synthesis of async controllers from STGs

Asynchronous circuit Aout delay delay Ain C C L logic L logic L logic L C C Rin delay Rout EMICRO 2016 Synthesis of async controllers from STGs

Asynchronous latches: C element
Vdd A B C A B C B A C B A A B C+ C C C A B Gnd EMICRO 2016 Synthesis of async controllers from STGs

Data-path / Control L logic L logic L logic L Rin Rout CONTROL Ain Aout EMICRO 2016 Synthesis of async controllers from STGs

Asynchronous modules DATA PATH Data IN Data OUT start done req in req out CONTROL ack in ack out Signaling protocol: reqin+ start+ [computation] done+ reqout+ ackout+ ackin+ reqin- start [reset] done- reqout- ackout- ackin- (more concurrency is also possible, e.g. by overlapping the return-to-zero phase of step i-1 with the evaluation phase of step i) EMICRO 2016 Synthesis of async controllers from STGs

Memory read cycle Valid address Address A A Valid data Data D D Transition signaling, 4-phase EMICRO 2016 Synthesis of async controllers from STGs

Control specification
B+ A- B A input B output B- Signal Transition Graph (STG) EMICRO 2016 Synthesis of async controllers from STGs

B+ A B A- B- Assumption: the environment meets the specification EMICRO 2016 Synthesis of async controllers from STGs

B- A B A- B+ EMICRO 2016 Synthesis of async controllers from STGs

B+ A C+ C C A- B- B C- EMICRO 2016 Synthesis of async controllers from STGs

B+ A C+ C C A- B B- C- EMICRO 2016 Synthesis of async controllers from STGs

Ri+ Ao+ Ri- Ao- Ro+ Ai+ Ro- Ai- Ri Ro Ao Ai FIFO cntrl STG (Petri Net) EMICRO 2016 Synthesis of async controllers from STGs

Ri+ Ro+ Ri Ro Ao Ai FIFO cntrl Ao+ Ai+ Ri- Ro- Ao- Ai- EMICRO 2016 Synthesis of async controllers from STGs

Ri+ Ao+ Ri- Ao- Ro+ Ai+ Ro- Ai- Ri Ro Ao Ai FIFO cntrl C Ri Ro Ai Ao EMICRO 2016 Synthesis of async controllers from STGs

A simple filter: specification
Ain Rin IN y := 0; loop x := READ (IN); WRITE (OUT, (x+y)/2); y := x; end loop filter Aout Rout OUT EMICRO 2016 Synthesis of async controllers from STGs

A simple filter: block diagram
x y + control Rin Ain Rout Aout Rx Ax Ry Ay Ra Aa IN OUT x and y are level-sensitive latches (transparent when R=1) + is a bundled-data adder (matched delay between Ra and Aa) Rin indicates the validity of IN After Ain+ the environment is allowed to change IN (Rout,Aout) control a level-sensitive latch at the output EMICRO 2016 Synthesis of async controllers from STGs

A simple filter: control spec.
x y + control Rin Ain Rout Aout Rx Ax Ry Ay Ra Aa IN OUT Rin+ Ain+ Rin- Ain- Rx+ Ax+ Rx- Ax- Ry+ Ay+ Ry- Ay- Ra+ Aa+ Ra- Aa- Rout+ Aout+ Rout- Aout- EMICRO 2016 Synthesis of async controllers from STGs

A simple filter: control impl.
Rin Ain Rx Ax Ry Ay Aa Ra Aout Rout Rin+ Ain+ Rin- Ain- Rx+ Ax+ Rx- Ax- Ry+ Ay+ Ry- Ay- Ra+ Aa+ Ra- Aa- Rout+ Aout+ Rout- Aout- EMICRO 2016 Synthesis of async controllers from STGs

Control: observable behavior
Rin Ain Rx Ax Ry Ay Aa Ra Aout Rout z Rin+ Ain- Rin- Aa- Ain+ Ra- Rx+ Ry- z- Ax- Rx- Ay+ Ay- Ax+ Ra+ Aa+ Rout+ Aout+ z+ Rout- Aout- Ry+ EMICRO 2016 Synthesis of async controllers from STGs

x x y y z z Environment Circuit z+ x- x+ y+ z- y- Signal Transition Graph (STG) EMICRO 2016 Synthesis of async controllers from STGs

x y z z+ x- x+ y+ z- y- EMICRO 2016 Synthesis of async controllers from STGs

Taking delays into account
x+ x- y+ y- z+ z- x z y x’ z’ Delay assumptions: Environment: 3 times units Gates: 1 time unit events: x+  x’-  y+  z+  z’-  x-  x’+  z-  z’+  y-  time: EMICRO 2016 Synthesis of async controllers from STGs

x+ x- y+ y- z+ z- 1 x y 1 z very slow Delay assumptions: unbounded delays EMICRO 2016 Synthesis of async controllers from STGs

z+ x- 1 x x+ y+ z- y 1 z y- very slow Delay assumptions: unbounded delays EMICRO 2016 Synthesis of async controllers from STGs

z+ x- 1 x 1 x+ y+ z- y 1 z y- very slow Delay assumptions: unbounded delays EMICRO 2016 Synthesis of async controllers from STGs

z+ x- 1 x 1 x+ y+ z- y 1 1 z y- very slow Delay assumptions: unbounded delays EMICRO 2016 Synthesis of async controllers from STGs

z+ x- failure!!!!! 1 x x+ y+ z- y 1 1 z y- very slow Delay assumptions: unbounded delays EMICRO 2016 Synthesis of async controllers from STGs

Delay models for async. circuits
Bounded delays (BD): realistic for gates and wires. Technology mapping is easy, verification is difficult Speed independent (SI): Unbounded (pessimistic) delays for gates and “negligible” (optimistic) delays for wires. Technology mapping is more difficult, verification is easy Delay insensitive (DI): Unbounded (pessimistic) delays for gates and wires. DI class (built out of basic gates) is almost empty Quasi-delay insensitive (QDI): Delay insensitive except for critical wire forks (isochronic forks). Formally, it is the same as speed independent In practice, different synthesis strategies are used BD DI SI  QDI EMICRO 2016 Synthesis of async controllers from STGs

Synthesis of asynchronous controllers from STGs
EMICRO 2016 Synthesis of async controllers from STGs

x y z Environment Circuit z+ x- x+ y+ z- y- Signal Transition Graph (STG) EMICRO 2016 Synthesis of async controllers from STGs

Specification (STG) Reachability analysis State Graph State encoding SG with CSC Design flow Boolean minimization Next-state functions Logic decomposition Decomposed functions Technology mapping Gate netlist EMICRO 2016 Synthesis of async controllers from STGs

x y z z+ x- x+ y+ z- y- EMICRO 2016 Synthesis of async controllers from STGs

State Graph Generation
xyz 000 y- x+ 100 y+ z+ 101 110 111 z+ x- x- 001 011 y+ x+ y+ z- y- z- 010 EMICRO 2016 Synthesis of async controllers from STGs

Next-state functions xyz 000 x+ 100 y+ z+ 101 110 111 x- 001 011 z- 010 y- EMICRO 2016 Synthesis of async controllers from STGs

Next-state functions x Env y z In this particular implementation, the circuit generates x and z and the environment generates y. EMICRO 2016 Synthesis of async controllers from STGs

VME bus DSr LDS LDTACK D DTACK Read Cycle Device LDS LDTACK D DSr DSw DTACK VME Bus Controller Data Transceiver Bus EMICRO 2016 Synthesis of async controllers from STGs

STG for the READ cycle DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- D LDS DSr VME Bus Controller LDTACK DTACK EMICRO 2016 Synthesis of async controllers from STGs

Choice: Read and Write cycles
DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DTACK- DSw+ D+ LDS+ LDTACK+ D- DTACK+ DSw- LDS- LDTACK- DTACK- EMICRO 2016 Synthesis of async controllers from STGs

Choice: Read and Write cycles
DTACK- DSr+ LDS+ LDTACK+ D+ DTACK+ DSr- D- LDS- LDTACK- DSw+ DSw- EMICRO 2016 Synthesis of async controllers from STGs

Circuit synthesis Goal: Derive a hazard-free circuit under a given delay model EMICRO 2016 Synthesis of async controllers from STGs

Speed independence Delay model Unbounded gate / environment delays Certain wire delays shorter than certain paths Conditions for implementability: Consistency Complete State Coding Persistency EMICRO 2016 Synthesis of async controllers from STGs

STG for the READ cycle DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- D LDS DSr VME Bus Controller LDTACK DTACK EMICRO 2016 Synthesis of async controllers from STGs

Binary encoding of signals
LDS = 0 LDS = 1 LDS - LDS + DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- DSr+ DTACK- LDTACK+ LDS- LDS- LDS- DSr+ DTACK- D+ D- DTACK+ DSr- EMICRO 2016 Synthesis of async controllers from STGs

Binary encoding of signals
10000 DSr+ DTACK- LDS+ LDTACK- LDTACK- LDTACK- 10010 DSr+ DTACK- 01100 00110 LDTACK+ LDS- LDS- LDS- DSr+ DTACK- 10110 01110 10110 D+ D- DTACK+ DSr- (DSr , DTACK , LDTACK , LDS , D) EMICRO 2016 Synthesis of async controllers from STGs

Next-state functions DSr DTACK LDS LDTACK D D DSr DTACK LDS LDTACK D LDS DSr VME Bus Controller LDTACK DTACK DSr DTACK LDS LDTACK D EMICRO 2016 Synthesis of async controllers from STGs

Next-state functions DSr DTACK LDS LDTACK D D DSr DTACK LDS DSr LDS LDS VME Bus Controller LDTACK LDTACK DTACK D DSr DTACK LDS LDTACK D EMICRO 2016 Synthesis of async controllers from STGs

Excitation / Quiescent Regions
ER (LDS+) ER (LDS-) QR (LDS+) QR (LDS-) LDS- LDS+ EMICRO 2016 Synthesis of async controllers from STGs

Next-state function for LDS
0  1 LDS- LDS+ 0  0 1  1 10110 1  0 EMICRO 2016 Synthesis of async controllers from STGs

Next-state function for LDS
5-variable Karnaugh map LDS = 0 LDS = 1 DTACK DSr D LDTACK 00 01 11 10 DTACK DSr D LDTACK 00 01 11 10 - 1 - - - 1 - - - - - - - - - - - - - 1 1 1 - - 0/1? EMICRO 2016 Synthesis of async controllers from STGs

Concurrency reduction
DSr+ LDS+ LDS- LDS- LDS- 10110 10110 EMICRO 2016 Synthesis of async controllers from STGs

Concurrency reduction
DSr+ DTACK- LDS+ LDTACK+ D+ DTACK+ DSr- D- LDTACK- LDS- D LDS DSr VME Bus Controller LDTACK DTACK Not always acceptable: the environment cannot be modified EMICRO 2016 Synthesis of async controllers from STGs

State encoding conflicts
LDS+ LDTACK- LDTACK+ LDS- 10110 10110 EMICRO 2016 Synthesis of async controllers from STGs

Signal Insertion CSC- CSC+ LDS+ LDTACK- LDTACK+ LDS- 101101 101100 D- DSr- EMICRO 2016 Synthesis of async controllers from STGs

Complex-gate implementation

Implementability conditions
Consistency Rising and falling transitions of each signal alternate in any trace Complete state coding (CSC) Next-state functions correctly defined Persistency No event can be disabled by another event (unless they are both inputs) EMICRO 2016 Synthesis of async controllers from STGs

Implementability conditions
Consistency + CSC + persistency There exists a speed-independent circuit that implements the behavior of the STG (under the assumption that any Boolean function can be implemented with one complex gate) EMICRO 2016 Synthesis of async controllers from STGs

Persistency 100 000 001 a- c+ b+ a c b a c b is this a pulse ? Speed independence  glitch-free output behavior under any delay EMICRO 2016 Synthesis of async controllers from STGs

Example a+ b+ c+ d+ a- b- d- c- 0000 1000 1100 0100 0110 0111 1111 1011 0011 1001 0001 a+ b+ c+ a- b- c- d- d+ EMICRO 2016 Synthesis of async controllers from STGs

ab cd 00 01 11 10 1 0000 1000 1100 0100 0110 0111 1111 1011 0011 1001 0001 a+ b+ c+ a- b- c- d- d+ ER(d+) ER(d-) EMICRO 2016 Synthesis of async controllers from STGs

ab 0000 1000 1100 0100 0110 0111 1111 1011 0011 1001 0001 a+ b+ c+ a- b- c- d- d+ cd 00 01 11 10 00 1 01 1 1 1 1 11 1 10 Complex gate EMICRO 2016 Synthesis of async controllers from STGs

ab cd 00 01 11 10 1 d 00 c 1 01 1 1 1 1 11 a 1 10 L c d Complex gate a EMICRO 2016 Synthesis of async controllers from STGs

Implementation with C elements
R S z • • •  S+  z+  S-  R+  z-  R-  • • • S (set) and R (reset) must be mutually exclusive S must cover ER(z+) and must not intersect ER(z-)  QR(z-) R must cover ER(z-) and must not intersect ER(z+)  QR(z+) EMICRO 2016 Synthesis of async controllers from STGs

ab 0000 1000 1100 0100 0110 0111 1111 1011 0011 1001 0001 a+ b+ c+ a- b- c- d- d+ cd 00 01 11 10 00 1 01 1 1 1 1 11 1 10 S d C R EMICRO 2016 Synthesis of async controllers from STGs

0000 1000 1100 0100 0110 0111 1111 1011 0011 1001 0001 a+ b+ c+ a- b- c- d- d+ but ... S d C R EMICRO 2016 Synthesis of async controllers from STGs

Assume that R=ac has an unbounded delay 0000 1000 1100 0100 0110 0111 1111 1011 0011 1001 0001 a+ b+ c+ a- b- c- d- d+ Starting from state 0000 (R=1 and S=0): a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ; R+ disabled (potential glitch) S d C R EMICRO 2016 Synthesis of async controllers from STGs

ab 0000 1000 1100 0100 0110 0111 1111 1011 0011 1001 0001 a+ b+ c+ a- b- c- d- d+ cd 00 01 11 10 00 1 01 1 1 1 1 11 1 10 C S R d Monotonic covers EMICRO 2016 Synthesis of async controllers from STGs

C-based implementations
R d c d C b a c weak d c weak d a a b generalized C elements (gC) EMICRO 2016 Synthesis of async controllers from STGs

Speed-independent implementations
Implementability conditions Consistency Complete state coding Persistency Circuit architectures Complex (hazard-free) gates C elements with monotonic covers ... EMICRO 2016 Synthesis of async controllers from STGs

Petrify: a tool for the synthesis of Petri nets and asynchronous controllers EMICRO 2016 Synthesis of async controllers from STGs

petrify Initially created in 1992 to generate Petri nets from Labelled Transition Systems Later extended for the synthesis of asynchronous controllers (including state encoding, technology mapping, relative timing, …) Widely used in the asynchronous community for the synthesis of controllers Available (binary and tutorial) at: EMICRO 2016 Synthesis of async controllers from STGs

petrify: example lr+ rr+ lr Cntrl rr la+ ra+ la ra lr- rr- la- ra- EMICRO 2016 Synthesis of async controllers from STGs

petrify: input format lr+ rr+ .inputs lr ra .outputs la rr .graph rr+ ra+ la+ rr- ra- la+ lr- la- lr+ lr+ la+ rr+ lr- la- rr- ra+ rr- la- ra- rr+ .marking { <la-,lr+> <ra-,rr+> } .end la+ ra+ lr- rr- la- ra- EMICRO 2016 Synthesis of async controllers from STGs

petrify: visualization
lr+ rr+ la+ ra+ lr- rr- la- ra- EMICRO 2016 Synthesis of async controllers from STGs

petrify: generation of state graph

petrify: state encoding

petrify: logic synthesis
[la] = rr*csc0’; [rr] = csc0’; [csc0] = csc0*(lr’ + ra) + lr’*ra; EMICRO 2016 Synthesis of async controllers from STGs

petrify: technology mapping
# gate and2_1 [la] = rr*csc0'; # gate inv [rr] = csc0'; # gate c_element1 [csc0] = ra*(lr' + csc0) + lr'*csc0; (Note: tech mapping is not that easy. Be careful with glitches) EMICRO 2016 Synthesis of async controllers from STGs

not covered … State encoding: Signals must be inserted preserving consistency and persistency Technology mapping: New hazard-free signals must be inserted The new signals should help in simplifying logic Relative timing: Introduce assumptions on the ordering of concurrent events EMICRO 2016 Synthesis of async controllers from STGs

No Hazards abcx 1000 1100 b+ 1 1 1 1 a b c x 0100 a- 0110 c+ EMICRO 2016 Synthesis of async controllers from STGs

Decomposition May Lead to Hazards
abcx 1000 1100 b+ 0100 a- 0110 c+ 1 1 1 1 1 1 a b z c x EMICRO 2016 Synthesis of async controllers from STGs

Strategy for logic decomposition
Each decomposition defines a new internal signal Method: Insert new internal signals such that After resynthesis, some large gates are decomposed The new specification is hazard-free Generate candidates for decomposition using standard logic factorization techniques: Algebraic factorization Boolean factorization (boolean relations) EMICRO 2016 Synthesis of async controllers from STGs

Decomposition example
1001 1011 1000 1010 0001 0000 0101 0010 0100 0110 0111 0011 y- y+ x- x+ w+ w- z+ z- y- z- w- y+ x+ z+ x- w+ EMICRO 2016 Synthesis of async controllers from STGs

x y w z 1001 1011 1000 1010 0001 0000 0101 0010 0100 0110 0111 0011 y- y+ x- x+ w+ w- z+ z- y- yz=1 yz=0 1001 1011 z- w- 1000 0001 w+ y+ w- z- x+ 1010 0000 0101 0011 w- y+ x+ z- 0010 0100 x- x+ y+ z+ 0110 0111 EMICRO 2016 Synthesis of async controllers from STGs

x y w z y- s 1001 1011 z- s- 1001 w+ 1000 z- y+ s- w- 0011 1000 0001 1010 y+ s- w- z- x+ x- 1010 0000 0101 w- y+ x+ z- 0111 0010 0100 x+ y+ s+ s=0 z+ 0111 0110 EMICRO 2016 Synthesis of async controllers from STGs

1001 1011 z- s- s- 1000 1001 w+ z- y+ s- w- z- w- w+ 0011 1000 0001 1010 y+ s- w- z- x+ x- 1010 0000 0101 y+ x+ x- w- y+ x+ z- 0111 0010 0100 x+ y+ s+ s+ z+ s=0 z+ 0111 0110 EMICRO 2016 Synthesis of async controllers from STGs

x y w z 1001 1011 1000 1010 0001 0000 0101 0010 0100 0110 0111 0011 y- y+ x- x+ w+ w- z+ z- y- 1001 1011 z- w- 1000 0001 w+ y+ w- z- x+ 1010 0000 0101 0011 w- y+ x+ z- 0010 0100 x- x+ y+ z+ 0110 0111 yz=0 yz=1 EMICRO 2016 Synthesis of async controllers from STGs

1001 1011 s- s- 1001 w+ z- w- 0011 1000 0001 z- w- w+ y+ w- z- x+ x- 1010 0000 0101 w- y+ x+ z- y+ x+ x- 0111 0010 0100 x+ y+ s+ s+ s=0 z+ z+ 0111 0110 z- is delayed by the new transition s- ! EMICRO 2016 Synthesis of async controllers from STGs

x y w z s=1 1001 1011 s- 1001 w+ z- w- 0011 1000 0001 y+ w- z- x+ x- 1010 0000 0101 w- y+ x+ z- 0111 0010 0100 x+ y+ s+ y y y y y y y s=0 z+ 0111 0110 EMICRO 2016 Synthesis of async controllers from STGs

Burst mode FSM Close to synchronous FSMs with binary encoded I/O Work in bursts: Input transitions fire Output transitions fire State signals change Mostly limited to fundamental mode: next input burst cannot arrive before stabilization at the outputs Extended Burst Mode (XBM) allows certain degree of concurrency a Control x b y c s1 b-/x- a+b+/y+ a-/x+y- s2 s4 c-/y+ c+/y- s3 EMICRO 2016 Synthesis of async controllers from STGs

Conclusions Controllers are the tiny (and smart) components of asynchronous systems. Controllers may contain intricate relationships among events: concurrency, causality, choice. Design automation is required. STGs are a friendly formalism for specification: they resemble waveforms. EMICRO 2016 Synthesis of async controllers from STGs

Gate vs wire delay models
Gate delay model: delays in gates, no delays in wires Wire delay model: delays in gates and wires EMICRO 2016 Synthesis of async controllers from STGs

Synthesis of asynchronous controllers from Signal Transition Graphs:

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