1. FIELD EFFECT TRANSISTOR
POWER POINT PRESENTATION BY:-POONAM SHARMA
LECTURER ELECTRICAL
G.P. MANESAR

2. Field-Effect Transistors (FETs)
FET basic operational theory FET basic operational theory
•The current controlled mechanism (drain current) is based on electric field established by the voltage applied to the control terminal (gate).
•Current is only conducted by only one type of carrier “ electrons or holes” (that is why sometimes FET is called unipolar transistors. Another type is the insulated gate FET or IGFET.
•Why MOS (Metal-Oxide) Transistors?
•Very small (smaller silicone area on the IC)
•Simple to manufacture
•No need for biasing resistors.
•Used in VLSI (very-large-scale integration)
•The enhancement type MOSFET is the most significant semiconductor devise available today.

3. Field-Effect Transistors (FETs)

4. Field-Effect Transistor (FET)
Metal-oxide semiconductor field-effect transistor (MOSFET) has been extremely popular since the late 1970s.
Compared to BJTs, MOS transistors:
Can be made smaller /higher integration scale
Easier to fabricate /lower manufacturing cost
Simpler circuitry for digital logic and memory
Inferior analog circuit performance (lower gain)
Most digital ICs use MOS technology
Recent trend: more and more analog circuits are implemented in MOS technology for lower cost integration with digital circuits in a same chip

5. Field-Effect Transistors (FETs) Device Structure
Four Terminals: Gate, Drain, Source, Body
Unlike the BJT, the MOSFET is normally constructed as a symmetrical device.
The name of Metal-Oxide-Semiconductor is apparent from the structure.
Typically, L = 0.15 to 10 µm, W = 0.3 to 500µm, the thickness of the oxide layer is in the range of 0.02 to 0.1 µ m.
The minimum value of L achievable in a particular MOS technology is often referred as the feature size of the technology.
State-of-the-art: Intel Pentium 4uses 0.13 µm technology
Modern technology uses poly-silicon which has high conductivity, instead of metal to form the gate.

6. Physical Operation of Enhancement MOSFET
Operation with No Gate Voltage
With no bias applied to the gate, two back-to-back diodes exist in series between drain and source. The two back-to-back diodes prevent current conduction from drain to source when a voltage vDS is applied. The resistance is of the order of 10^12 ohms
Creating a Channel for Current Flow
If S and D are grounded and a positive voltage is applied to G, the holes are repelled from the channel region downwards, leaving behind a carrier-depletion region.
Further increasing VG attracts minority carrier ( electrons) from the substrate into the channel region. When sufficient amount of electrons accumulate near the surface of the substrate under the gate, an n region is created-called as the inversion layer.

7. Physical Operation of Enhancement MOSFET Applying a Small vDS
When a small potential is applied across the Gate and source, it pushes away the holes towards the substrate and attract electrons from the Drain and Source into the channel region. When sufficient electrons are formulated beneath the Gate area, current flows between the Drain and the Source. (Basically the holes are pushed away in N channel – NMOS type to be replaced by the electrons from both the Source and the Drain creating a channel of N majority causing current to flow from Drain to Source.

8. Field-Effect Transistors (FETs) - Enhancement Type
The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

9. Field-Effect Transistors (FETs) - Enhancement Type
An NMOS transistor with vGS > Vt and with a small vDS applied. The device acts as a conductance whose value is determined by vGS. Specifically, the channel conductance is proportional to vGS - Vt, and this iD is proportional to (vGS - Vt) vDS. Note that the depletion region is not shown (for simplicity).