1. MCP Electronics Time resolution, costs

2. MCP signals simulation:
200ps rise time
400ps fall time
Shot noise %
Output noise %
Signal/noise=30
Sampling frequency GHz

3. MCP signals:
200ps rise time

5. Performance sensitivity to feature size
1 Input analog bandwidth limitations:
- IO pads ESD protections Yes (RF diodes) +
- Effective input signal load (R, L, C) No
- Open switches parasitics Yes +
2 Sampling process
- Switch resistance Yes +
- Storage capacitance value No (kT/C limited)
- Number of caps at a time No (constant ~ 4)
- Aperture jitter Yes
- Dynamic range Yes Voltage supply dep .-

6. DLL’s Architecture (25ps sampling)
625 MHz clock in
16 cells
125ps
100ps
100ps
100ps
100ps
150ps
175ps
16 * 4 = 64 cells

7. Costs vs Sampling frequency
Assuming sampling period proportionnal to feature size,
scaled to 250nm 90
130
250
180

8. Costs vs time resolution
Assuming sampling period proportional to feature size
scaled to 25mm2 design in 250nm 90
130
250
180