1. Chis status report

2. Next submission
Due date 16 february
Process 0.13um IBM (8RF-DM)

3. Specs 4 Channels / 2 Token readouts / 1 DLL 256 cells/channels
Max power = 100mW/channels
Conversion time = 2us
Readout time = 1us/channels

4. Improvements New IBM design kit 1.6.2.4 (Redraw layouts)
Trigger at the input (New Comparators)
Increased range (New buffer)
Faster and better AtoD conversion
Faster read-out (New D-Flipflop)
Two-edges DLL (To do)
Removal of the DC current in the IO pads

5. Trigger schematic

6. Internal Trigger trigger output- control write switch latency 2-3 ns
threshold levels
simulated pulse (stalactite)
reset trigger – restart writing process

7. -Works for both + and – pulses
Internal Trigger
trigger output
threshold levels
simulated pulse (stalagmite)
reset trigger – restart writing process
latency 1-2 ns
-Works for both + and – pulses
-Acceptable latency (each sampling capacitor is rewritten every ~ 25 ns)
-Keep external trigger option in addition

8. A to D conversion Logic setup:
when Reset = 1, mux sends gnd to Clock input on register, stopping count

9. simulation -> rollover protection
2.5 GHz clock
comparator output in red (stays high)
counting stops when 13th bit goes high (400ps*4096=1.64us)

10. New input structure Sampling capacitance with read and write switches
Rail to rail voltage follower used as a buffer for the stored value.

11. Buffer
1V of linear input dynamic

12. Sampling
Sampling
Buffered value
Capacitance value

13. Phase detector

14. The output1 fires when input1 comes first and vice versa
The output1 fires when input1 comes first and vice versa. The pulse width depends on the delay between the two input pulse.