1. Characteristics of Reconfigurable Hardware
Reconfigurable Hardware for on-shore DAQ of km3 scale Neutrino Telescopes
Hardware vs. Software
Characteristics of Reconfigurable Hardware
Opportunities for DAQ
Tasos Belias

2. Application specific Hardware vs. Software
fast
“local execution”
fine-grained parallelism
no extraneous connections
compact
operators tailored to function
simple control
direct wire connections
between operators
Software
Slow
sequential execution
overhead time “interpreting”
operations
Inefficient Area
fixed width operators, may not match problem
general operators, bigger than required
area to store instructions, control execution
Fast But Fixed!
But Flexible!
Combine both through Reconfigurable Hardware
Tasos Belias

3. Reconfigurable Hardware FPGA-Advantage
Customization of operator type, width, and interconnect of I/O data.
Exploit low overhead and parallelism of application.
Exploit cases where operation can be bound and then reused a large number of times.
Adaptation to any switch-fabric protocol for data routing to external resources.
Tasos Belias

4. n-Telescope on-shore DAQ tasks
Key to the project: simultaneous, dead time-less readout of O(10000) channels and signal processing tasks
integrity check of raw data,
apply calibrations to raw data,
classification algorithms using raw data,
as well as network and protocol layer processing for
distribution / routing of raw data to processing nodes.
To achieve these tasks: use a system that provides both traditional and reconfigurable hardware
Scalability
Flexibility
Components Off The Shelf-Implementations
Tasos Belias

5. KM3NeT targeted Implementations
Accumulate deep-sea data on dedicated links
Physical medium interface
Optical / Electrical converter, Small form-factor pluggable transceivers
Protocol layer
MAC core, Custom link
Check and Filter Data
FPGA-centric memory & processing
Standard FPGA interconnects ( such as Rocket I/O)
Concurrent, adaptable filtering schemes
Physics-interest filters, GRBs, SNs,…
Format and Route to processing farms
Adapt to any standard switch-fabric protocol
Tasos Belias

6. Possible Mixed Architecture
PCIe
I/O Scaling
21GB/s (peak)
System Memory
FSB /
FPGA
North Bridge
10GB/s
PCIe
South Bridge
FSB 8.5GB/s
FSB /
FPGA
10GB/s
Conventional processor centric MP host
Host for Power / Control
Route downstream
Data Monitoring & Visualization
Reconfigurable data centric system
Data Acquisition
Check, Calibrate, Classify
Real-Time & Deterministic
Tasos Belias 6

7. All on one slide Reconfigurable architectures - FPGAs
computing in hardware
programmable like software
more computation per unit area than processors
efficient where processors are inefficient
Heterogeneous architectures (mix processors, reconfigurable)
“general-purpose” and “application-targeted” processing components
Exploiting these architectures  new strategies for DAQ of km3 scale n-Telescope
Tasos Belias