1. Computer Architecture and Organization: L11: Design Control Lines
By: A. H. Abdul Hafez
CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
December 6, 2018

2. Outlines Simple example: revision to bus system
Registers and Memory Control lines circuits
Design of TR and AR registers
Design of memory read and write lines
Common bus selection lines
Accumulator logic design
AC control lines
Adder logic design
End
CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
December 6, 2018

3. CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
December 6, 2018

4. T0’T1’T2’ IEN (FGI + FGO): R ← 1
Table (5-6) Control Functions and Microoperations for the basic computer (Mano computer)
Register Reference D7 I’ T3 = r
IR( I ) = Bi [bit in IR (0-11) that specifies the operation] r:
SC ← 0
CLA
rB11:
AC ← 0
CLE
rB10:
E ← 0
CMA
rB9:
AC ← AC
CME
rB8:
E ← E
CIR
rB7:
AC ← shr AC, AC(15) ← E, E← AC (0)
CIL
rB6:
AC ← shl AC, AC(0) ← E, E← AC (15)
INC
rB5:
AC ← AC+1
SPA
rB4:
If (AC (15)=0) then (PC← PC+1)
SNA
rB3:
If (AC (15)=1) then (PC← PC+1)
SZA
rB2:
If (AC =0) then (PC← PC+1)
SZE
rB1:
If (E=0) then (PC← PC+1)
HLT
rB0:
S← 0 (S is a start-stop flip-flop)
Fetch
R’T0:
R’T1:
AR ← PC
IR ← M[AR], PC ← PC + 1
Decode
R’T2:
D0….D7 ← IR (12-14), I ← IR (15),
AR ← IR (0-11)
Indirect
D7’IT3:
AR ← M[AR]
Interrupt
T0’T1’T2’ IEN (FGI + FGO): R ← 1
RT0:
AR ← 0, TR ← PC
RT1:
M[AR] ← TR, PC ← 0
RT2:
PC ← PC + 1, IEN ← 0, R ← 0, SC ← 0
Memory Reference
AND
D0T4:
D0T5:
DR ← M[AR]
AC← AC ^ DR, SC← 0
ADD
D1T4:
D1T5:
AC← AC ^ DR, E ← Cout, SC← 0
LDA
D2T4:
D2T5:
DR← M[AR]
AC← DR, SC← 0
STA
D3T4:
M[AR]← AC, SC← 0
BUN
D4T4:
PC← AR, SC← 0
BSA
D5T4:
D5T5:
M[AR] ← PC, AR← AR+1
ISZ
D6T4:
D6T5:
D6T6:
DR ← DR + 1
M[AR] ← DR, if DR=0 then
PC ← PC + 1
Input-output
D7 I T3 =p (common for all input-output instructions)
IR( I ) = Bi [bit in IR (6-11) that specifies the instructions] p:
SC ← 0
INP
pB11:
AC(0-7) ←INPR, FGI ← 0
OUT
pB10:
OUTR ←AC (0-7), FGO ← 0
SKI
pB9:
if (FGI=1) then (PC ←PC + 1)
SKO
pB8:
if (FGO=1) then (PC ←PC + 1)
ION
pB7:
IEN ← 1
IOF
pB6:
IEN ←0

5. Design of Basic Computer
The proposed basic computer consists of the following hardware components:
1- A memory unit with 4096 words of 16 bits each.
2- Nine registers : AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC.
3- Seven Flip Flops: I, S, E, R, IEN, FGI, and FGO.
4- Two decoders: 3-to-8 op-code decoder and 4-to-16 timing decoder.
5- 16-bit common bus.
6- Control logic gates.
7- Adder and logic circuit connected to the input of the accumulator.
December 6, 2018
CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

6. S E R
IEN
FGI
FGO DR
instruction register (IR) AC 15
11-0
3x8
decoder
Control
logic
gates D0
... D7 I
T15
... T0
. . .
4x6
decoder
(INR)
4-bit
Sequence
Counter (SC)
(CLR)
Clock

7. Control Lines: Simple Example
The multiplexer selects one of the four registers as the source register. Control lines for the MUX are driven by external circuitry. The data is made available to all registers, but only one actually loads the data. Again, external hardware generates load signals for the four registers such that no more than one is active at any given time.
The symbolic statement for a bus transfer may mention the bus or its presence may be implied in the statement. When bus is included in the statement we write:
BUS  C, A BUS (however it is A C)
P: A  B
Q: A  C
R: B  D
S: C  A
T: D  C
U: D  B
CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
December 6, 2018

8. Registers and Memory Control lines circuits
Note: To design the control circuit for any register or memory input control lines, we have to scan table (5-6) to find the required control functions for each control line.
Ex: Design of TR
After the scanning of table (5-6), TR is modified only by the microoperation
RTo: TR ← PC, So the control circuit will be 12 12
From Bus TR
To the Bus LD
CLK R To

9. Ex: Design of AR register
Scan table (5-6) for the transfer statements that change the content of AR:
R’T0: AR ← PC LD (AR)
R’T2: AR ← IR(0-11) LD (AR)
D’7IT3: AR ← M[AR] LD (AR)
LD(AR)= R’T0+R’T2+D’7IT3
RT0: AR ← 0 CLR (AR)
D5T4: AR ←AR+1 INR (AR) AR 12
From bus
to bus
clock T0
CLR
INR LD
D’7 I T3 T2 R D5 T4

10. Ex: Design of Memory Read and Write control circuits
Scanning the table, lead to the control functions for the Read and Write memory input lines:
Read= R’T1+D’7IT3+(D0+D1+D2+D6) T4
Write= RT1+D3T4+D5T4+D6T6
Memory
Read
Write Do D2 D6 D1 T4 R’ T1
D’7 I T3 R T6 D3 D5

11. Control circuit of single Flip Flop
Ex: For the IEN Flip Flop, table 5-6 shows that IEN may change as a result of the instructions: ION, IOF, and is reset at the end of the interrupt cycle. The control functions and microoperations are:
pB7: IEN←1 ION instruction
pB6: IEN←0 IOF instruction
RT2: IEN←0 ION instruction at the end of the interrupt cycle

12. Encoder for Bus Selection : Table. 5-6
Control of Common Bus
Encoder for Bus Selection : Table. 5-6
S0 = x1 + x3 + x5 + x7
S1 = x2 + x3 + x6 + x7
S2 = x4 + x5 + x6 + x7
x1 = 1 :
Control Function :
x2 = 1 :
x7 = 1 :
Same as Memory Read Control Function :
x1 = 1 corresponds to the bus connection of AR as a source
Encoder
Multiplexer
Bus Select
Input x1 x2 x3 x4 x5 x6 x7 So S1 S2

13. Design of Accumulator Logic Circuit
The circuits associated with the AC register are shown in the Figure below. The Adder has three inputs: one set of 16-bit from the output of the accumulator. Another set of 16-bit comes from the DR register. A third set of 8-bit comes from the INPR.
The AC is provided with three control lines: LD, INR, and CLR.

14. Design of AC Register
Search table 5-6 for the statements that change the content of AC. The statements, their control functions and the corresponding logic circuit are shown below. LD
INR
CLR
Fig. (5-20)

15. Adder and Logic Circuit
This circuit consists of 16 single-bit adder and logic duplicated circuits. The carry output of the first stage is connected to the carry input of the next stage, and so on.
Stage 0
Stage 1
Stage 14
Stage15
Cout
Cin
AC (1)
AC (14)
AC (15)
DR (0)
DR (1)
DR (14) E
INPR (0)
INPR (1)
AC (0)
AC (0)
Detail connection of single stage

16. Adder and Logic circuit
COM
INPR DR
ADD
SHL
SHR FA J Q K LD
(Output of OR gate in Fig. 5-20)
(Fig.2-11) I i
AC(i)
Clock
AC(i-1)
AC(i+1)
From
bit(i) C
i+1
DR(i)

17. The end of the Lecture Thanks for your time Questions are welcome
CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU
December 6, 2018