1. Alex Saify Chad Reynolds James Aldorisio Brian Bischoff
UltraSPARC
Alex Saify
Chad Reynolds
James Aldorisio
Brian Bischoff

2. SPARC History 1987 debut: 32-bit, 36 MHz RISC specification, not a CPU
Early competition: Intel, Motorola

3. UltraSPARC Highlights
High integration
Huge installed user base
Backward compatibility
Multimedia extensions

4. Integer Execution Unit (IEU)
2 ALUs (number crunching) for arithmetic, logical, and shift operators
load - one cycle
store - two cycles

5. UltraSPARC Diagram

6. Floating Point Unit (FPU)
2 floating point instructions / cycle
The latency issue
square root
divide
Efficiency

7. Prefetch and Dispatch Unit
Fetches instructions before they are needed.
Can fetch instructions from all levels of the memory
Up to 12 instructions can be stored in the Instruction buffer until they are executed.
Uses a dynamic branch prediction scheme that is implemented in hardware.

8. Dynamic Branch Prediction
The most accurate form of branch prediction.
Guesses the destination of jump or branch instructions.
Predictions become more accurate over time.

9. 9 Stage Pipelining fetch decode grouping execution cache access load
miss
integer pipe wait
trap resolution
writeback

10. Registers SPARC v9 utilizes 64-bit registers
Processor has upwards of 144 registers

11. Register types Access Space Identifiers PSTATE Register
Registers contained form to general purpose integer registers as well as error and interrupt handling.
PSTATE Register

12. Ancillary State Registers
32 ASRs provided (0..31)
0..6 defined by the SPARC-V9 ISA
7..15 reserved for future use by architecture
available for use by implementations
Mainly consisting of status, control, and tick count registers.

13. Other UltraSPARC Registers
Global Registers
8 registers fall under this category
replaced by Interrupt Global Registers when the processor interrupts itself by writing to the SOFTINT register
increases the speed of the interrupt process

14. Instruction Set SPARC-V9 Instruction Set Extended Instruction Set
Visual Instruction Set (VIS)

15. SPARC-V9 Instruction Set
Includes general arithmetic instructions
Extension of the SPARC-V8 instruction set
Most of the instructions you would expect a processor to have

16. Extended Instruction Set
Power-down class
Graphics functionality class
Memory access class

17. Visual Instruction Set
What it’s used for
Why use it
2-D & 3-D modeling, audio, video, and imaging

18. Speed of the UltraSPARC
General Information
166 MHz and 200 MHz processors
7 ns and faster cycle time
0.25 CPI time
Bypassing

19. Speed of the UltraSPARC (cont.)
VIS Speeds
Up to 10 instructions per cycle
Potential of 2 billion operations/sec.

20. Uses for the UltraSPARC
High-End Multimedia
3D Design and Rendering (Toy Story)
Graphical Databases
Video Conferencing
Supercomputing
Server Solutions