1. A Step-By-Step Description of the Synplicity Flow
Section B
A Step-By-Step Description of
the Synplicity Flow
Andy Miller © Copyright 2000 Xilinx
- All Rights Reserved

2. Synplicity Flow - Start New Project
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3. Synplicity Flow - Start New Project1
Select...File->New 1 2
Set a New file location to be your SysGen
working directory 3
Click “OK” 4
Double-click on “Project
File” to accept it. 4 3 2
Andy Miller © Copyright 2000 Xilinx
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4. Synplicity Flow - Add SysGen Files
Now we add the System Generator
files to the new Synplicity Project. 1
Select.. File->Add File. 2
Note that the default HDL
is Verilog. Click on the down
arrow and select *.VHD. 1 3
Because you completed Step
2 on the previous page, a list
of SysGen VHD files will
appear in this window. 4 3 4
If they did not, then navigate
to where you told SysGen to
put them with the SysGen GUI. 2 5
Select the “Add All” button and
watch them appear in the
lower window. 5
Andy Miller © Copyright 2000 Xilinx
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5. Synplicity Flow - Add SysGen Files1
Now we add the System Generator
VHDL descriptions of any module
that cannot be mapped to a CORE
GeneratorTM core.
These files are stored in:
$Matlab12/toolbox/xilinx/sysgen/vhdl 2
Select the “Add All” button - this
it is the quickest way to get all the
components you need in one go!
NOTE: You will also see components
that you do not need; the synthesis
tool ignores everything except the
FIFO core, which I will mention
on the next foil.
Andy Miller © Copyright 2000 Xilinx
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6. Synplicity Flow - Order the Files1 2
Note that you must move the
conv_pkg using the same click and drag technique so that it occupies the second position in the list.
….. Sometimes I wonder if synthesis really is easier!
Andy Miller © Copyright 2000 Xilinx
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7. Synplicity Flow - Compile the design
Select RUN -> Compile to see
if the synthesis tool is happy with the files and their order.
At this stage, you may get an
ERROR from the xlfifo_core.vhd
file if you forgot to delete it.
Simply delete it and hit F7, or
repeat Step 1. 1 2
Andy Miller © Copyright 2000 Xilinx
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8. Synplicity Flow - Select Device1
Now you are almost ready to synthesize the design; you just need to choose the target device and identify where the output files will be placed. Select “Impl Options.” 2
Choose the target family.
(Note that only Xilinx Virtex/E/II
and Xilinx Spartan-II will work.)
Choose the part.
Choose the speed grade.
(Note -6 = slowest; -8 = fastest)
Choose the package.
Select the Options/Constraints tab. 3 4 5 6
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9. Synplicity Flow - Target the Output1
Select to where the target files are going to be written. 2
Select “OK.”
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10. Synplicity Flow - Synthesize the design1
Now Synthesize the design by hitting the RUN button.
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11. - Watch how it speeds along :o)
As Synplicity is running, it indicates what it is doing.
It can sometimes be in the mapping phase for a long time.
Andy Miller © Copyright 2000 Xilinx
- All Rights Reserved

12. Synplicity Flow - View the RTL diagram
When Synplicity has completed the design, click on this
icon to view the RTL (Register Transfer Level) view of the design. This is a logical
representation of the design, and there is normally a 1-to-1 correlation between the
blocks within the Simulink diagram and the Sythensis diagram.
Andy Miller © Copyright 2000 Xilinx
- All Rights Reserved

13. View the Technology Mapped Result
Now click on this icon to see how Synplicity has actually mapped the design.
It will be at this stage that you can sometimes notice the effect of NOT choosing
to use CORE Generator Cores.
If you use COREGen cores, you will not be able to navigate into the hierarchy using this icon.
Xlmult: This is a COREGen Core, and it cannot
be traversed with the hierarchy viewer because
the EDIF has been created by CORE Generator. The Synthesis tool treats this block as a black box.
Andy Miller © Copyright 2000 Xilinx
- All Rights Reserved

14. View the Technology Mapped Result
Now click on this icon to see how Synplicity has actually mapped the design.
At this stage, you can also sometimes notice the effect of NOT choosing
to use CORE Genenerator Cores.
If you use COREGen cores, you will not be able to navigate into the hierarchy using this icon.
(Press your “Page Down”
key to end the presentation.)