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Published byAndré Boisvert Modified over 6 years ago
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40-pin DIL BREAK-OUT HEADER (incl. 4x diff. pairs 2V5 LVDS ) 3 32
3x LEDs 3 32 6x POWER 2x GND pins 12x LEDs 3 2 2 6x FUSES SHIFT REG. 3 VME BASE ADDRESS A<31-24> 8 3 FPGA & PROM Xilinx Spartan3e XC3S1600E-5FGG400C 3 SW Buffers VME J2 SW CLKIN0 CLKIN1 NIM ECL 2 2 MPX PLL IN0 CLKIN select NIM TTL CLK Master DELAY 20x LEMO-00 IN2 8 8 4 4 IN4 40/80MHz select Buffers VME J1 4x Slave DELAYS 4 IN6 :2 CLKOUT0 CLKOUT1 2 NIM ECL 2 7 2x LEDs 7 X-TAL MHz OUT0 16 All POWER Monitor NIM TTL 8 8 OUT2 8 Data 4Mbx18 SRAM Address 7 OUT4 2 22 +5V +3V3 +2V5 +1V8 +1V2 -5V -2V OUT6 8 FUSES 16-pin AUX. CONNECTOR 16 ( incl. 2x diff. pairs 2V5 LVDS ) 16 6x DC-DC MOD. RECORD 6 8 SW J-TAG SW SHIFT REG. HEX SELECT 4 SERIAL NO. 8 SW EXT V IN 4 24 USB MCU SW USB MP-UCL, 18 August 2011
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