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VLSI Testing Lecture 8: Sequential ATPG

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1 VLSI Testing Lecture 8: Sequential ATPG
Dr. Vishwani D. Agrawal James J. Danaher Professor of Electrical and Computer Engineering Auburn University, Alabama 36849, USA IIT Delhi, Aug 21, 2013, 3:30-4:30PM Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

2 Lecture 8: Sequential ATPG
Contents Problem of sequential circuit ATPG Time-frame expansion Nine-valued logic ATPG implementation and drivability Complexity of ATPG Cycle-free and cyclic circuits Asynchronous circuits Summary Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

3 Lecture 8: Sequential ATPG
Sequential Circuits A sequential circuit has memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output Methods of sequential circuit ATPG Time-frame expansion methods Simulation-based methods Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

4 Example: A Serial Adder
An Bn 1 1 s-a-0 D 1 1 D X Cn Cn+1 X 1 Combinational logic Sn X FF Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

5 Lecture 8: Sequential ATPG
Time-Frame Expansion An-1 Bn-1 Time-frame -1 An Bn Time-frame 0 1 1 1 1 s-a-0 D X s-a-0 D D 1 1 Cn-1 1 D X Cn 1 D 1 Cn+1 X 1 Combinational logic Combinational logic 1 Sn-1 Sn X D FF Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

6 Concept of Time-Frames
If the test sequence for a single stuck-at fault contains n vectors, Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Vector -n+1 Vector -1 Vector 0 Fault Unknown or given Init. state State variables Next state Time- frame -n+1 Time- frame -1 Time- frame Comb. block PO -n+1 PO -1 PO 0 Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

7 Example for Logic Systems
FF1 B A FF2 s-a-1 Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

8 Five-Valued Logic (Roth) 0,1, D, D, X
A s-a-1 s-a-1 D D X X X FF1 FF1 X D D FF2 FF2 B X B X Time-frame -1 Time-frame 0 Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

9 Nine-Valued Logic (Muth) 0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X
A X s-a-1 s-a-1 0/1 X/1 X 0/X 0/X FF1 FF1 X 0/1 X/1 FF2 FF2 B X B 0/1 Time-frame -1 Time-frame 0 Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

10 Implementation of ATPG
Select a PO for fault detection based on drivability analysis. Place a logic value, 1/0 or 0/1, depending on fault type and number of inversions. Justify the output value from PIs, considering all necessary paths and adding backward time-frames. If justification is impossible, then use drivability to select another PO and repeat justification. If the procedure fails for all reachable POs, then the fault is untestable. If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can be justified, the the fault is potentially detectable. Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

11 Lecture 8: Sequential ATPG
Drivability Example (11, 16) (10, 15) (22, 17) (10, 16) d(0/1) = d(1/0) = 32 8 s-a-1 d(0/1) = 4 d(1/0) = d(0/1) = d(1/0) = 20 8 8 (5, 9) (4, 4) (17, 11) d(0/1) = 9 d(1/0) = (CC0, CC1) = (6, 4) (6, 10) d(0/1) = 120 d(1/0) = 27 8 FF d(0/1) = 109 d(1/0) = 8 CC0 and CC1 are SCOAP combinational controllabilities d(0/1) and d(1/0) of a line are effort measures for driving a specific fault effect to that line Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

12 Complexity of ATPG Synchronous circuit -- All flip-flops controlled by clocks; PI and PO synchronized with clock: Cycle-free circuit – No feedback among flip-flops: Test generation for a fault needs no more than dseq + 1 time-frames, where dseq is the sequential depth. Cyclic circuit – Contains feedback among flip-flops: May need 9Nff time-frames, where Nff is the number of flip-flops. Asynchronous circuit – Higher complexity! Smax Time- Frame max-1 Time- Frame max-2 S3 Time- Frame -2 S2 Time- Frame -1 S1 Time- Frame S0 max = Number of distinct vectors with 9-valued elements = 9Nff Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

13 Lecture 8: Sequential ATPG
Cycle-Free Circuits Characterized by absence of cycles among flip-flops and a sequential depth, dseq. dseq is the maximum number of flip-flops on any path between PI and PO. Both good and faulty circuits are initializable. Test sequence length for a fault is bounded by dseq + 1. Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

14 Lecture 8: Sequential ATPG
Cycle-Free Example Circuit F2 2 All faults are testable in this circuit. F3 F1 3 Level = 1 F1 F2 F3 Level = 1 2 3 s - graph dseq = 3 Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

15 Cyclic Circuit Example
Modulo-3 counter Z CNT F2 F1 s - graph F1 F2 Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

16 Lecture 8: Sequential ATPG
Modulo-3 Counter Cyclic structure – Sequential depth is undefined. Circuit is not initializable. No tests can be generated for any stuck-at fault. After expanding the circuit to 9Nff = 81, or fewer, time-frames ATPG program calls any given target fault untestable. Circuit can only be functionally tested by multiple observations. Functional tests, when simulated, give no fault coverage. Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

17 Adding Initializing Hardware
Initializable modulo-3 counter Z CNT F2 F1 s-a-0 s-a-1 CLR s-a-1 s-a-1 Untestable fault Potentially detectable fault s - graph F1 F2 Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

18 Lecture 8: Sequential ATPG
Benchmark Circuits Circuit PI PO FF Gates Structure Seq. depth Total faults Detected faults Potentially detected faults Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) Max. sequence length Total test vectors Gentest CPU s (Sparc 2) s1196 14 18 529 Cycle-free 4 1242 1239 3 99.8 100.0 313 10 s1238 14 18 508 Cycle-free 4 1355 1283 72 94.7 100.0 3 308 15 s1488 8 19 6 653 Cyclic -- 1486 1384 2 26 76 93.1 94.8 24 525 19941 s1494 8 19 6 647 Cyclic -- 1506 1379 2 30 97 91.6 93.4 28 559 19183 Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

19 Lecture 8: Sequential ATPG
Summary Combinational ATPG algorithms are extended: Time-frame expansion unrolls time as combinational array Nine-valued logic system Justification via backward time Cycle-free circuits: Require at most dseq + 1 time-frames Always initializable Cyclic circuits: May need 9Nff time-frames Circuit must be initializable Partial scan can make circuit cycle-free Asynchronous circuits: Not discussed See, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Chapter 8. Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

20 Lecture 8: Sequential ATPG
Problems to Solve Which type of circuit is easier to test? Circle one in each: Combinational or sequential Cyclic or cycle-free Synchronous or asynchronous What is the maximum number of input vectors that may be needed to initialize a cycle-free circuit with k flip-flops? Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

21 Lecture 8: Sequential ATPG
Solution Which type of circuit is easier to test? Circle one in each: Combinational or sequential Cyclic or cycle-free Synchronous or asynchronous What is the maximum number of input vectors that may be needed to initialize a cycle-free circuit with k flip-flops? k vectors. Because that is the maximum sequential depth possible. An example is a k bit shift register. Copyright 2001, Agrawal & Bushnell Lecture 8: Sequential ATPG

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