Presentation is loading. Please wait.

Presentation is loading. Please wait.

EE5780 Advanced VLSI Computer-Aided Design

Similar presentations


Presentation on theme: "EE5780 Advanced VLSI Computer-Aided Design"— Presentation transcript:

1 EE5780 Advanced VLSI Computer-Aided Design
VLSI Placement Prof. Shiyan Hu Office: EERC 518

2 Objectives Placement Problem Formulation Placement Technique
Motivation Definition Placement Technique General flow Quadratic program based wirelength optimization FM Partitioning

3 Placement Is Critical VLSI physical design is to design a layout satisfying the timing target Need to compute the physical locations of gates Interconnect delay is the dominating factor and it is proportional to wirelength

4 Placement Solution Placement is to determine the physical locations of all gates such that the gates are not overlapped and the total wirelength is minimized

5 Different Placements Bad Placement Good Placement

6 Problem Definition Input Output
Blocks (standard cells and macros) B1, ... , Bn The locations of some blocks are fixed Shapes and pin positions for each block Bi Nets N1, ... , Nm Output Coordinates (xi , yi) for block Bi The total wire length is minimized Subject to non-overlapping constraint

7 General Flow of Placement Technique
Wirelength optimization without considering non-overlapping constraint Adding constraints Partitioning to reduce overlaps

8 Wirelength Optimization
Write down the placement problem as an analytical mathematical problem (analytical placement) Quadratic placement Optimization target is to minimize the sum of wirelength Precisely sum of squared wirelength, also called cost Wirelength minimization problem can be formulated as a quadratic program It can be solved efficiently

9 2 gates to place and 2 pins are fixed
Example (I) x=100 x=200 x1 x2 2 gates to place and 2 pins are fixed

10 Example (II) x1 x2 x=100 x=200 Interpretation of matrices A and B
The diagonal values A[i,i] correspond to the number of connections to xi The off diagonal values A[i,j] are -1 if object i is connected to object j, 0 otherwise The values B[i] correspond to the sum of the locations of fixed objects connected to object i This approach can be easily extended to the two dimensional optimization

11 Exercise 1 Form the quadratic program and then the linear system for the following example x=200 x=500 x1 x2 x3

12 Exercise 2 How do we solve the linear system? How large is it?
It is a sparse linear system which can be efficiently solved using standard linear system solver such as the iterative conjugate gradient based approach.

13 Exercise 3 We choose to use square of wirelength in optimization target since the delay is a quadratic function of wirelength, but is it right target?

14 Exercise 4 When there are no fixed pins, what would the solution be?
Even with the fixed pins, there are still a lot of overlaps since in the quadratic program, non-overlapping constraint is not considered.

15 The Placement Technique
Quadratic program minimize the squared wirelength Partitioning reduce the overlap among gates

16 The Solution of Initial Quadratic Program

17 Partitioning Gates into Regions
After partitioning, restrict that the gates to the one side of the cut line can only be placed in that region The purpose of partitioning is to sparsify the placement, so it should try to balance the number of gates in each region Interconnects crossing the cut line should be few to reduce wirelength The FM partitioning technique will be described soon

18 Restrict Region During Wirelength Optimization
In the quadratic program for each region, add the additional constraint that the center of gravity of gates is the center of region. Center of Gravities

19 Exercise 5 Suppose that in the example of Exercise 1, the cutline is in the middle of the region and gate 1 and gate 2 are grouped into the left region. Form the quadratic program with the additional constraint. x=200 x=500 x1 x2 x3

20 (b) Placement with 4 regions
Placement Process (a) Placement with 1 region (b) Placement with 4 regions (c) Final placements

21 Partitioning Formulation
Given a set of interconnected gates, to generate two sets that are of roughly equal size, and such that the number of nets connecting the two sets is minimized.

22 FM Partitioning FM partitioning is a heuristic
- each object is assigned a gain, which is the amount of change in cut crossings that will occur if an object is moved from its current partition into the other partition. - objects are put into a sorted gain list - set the current region - at the current region, the object with the highest gain is selected and moved. - the moved object is locked - the gains of touched objects are recomputed gain lists are sorted again set the current region to the other region -1 2 -1 -2 -2 -1 1 -1 1

23 FM Partitioning -1 2 -1 -2 -2 -1 1 -1 1

24 FM Partitioning -1 -2 -2 -2 -1 -2 -2 -1 1 -1 1

25 FM Partitioning -1 -2 -2 -2 -1 -2 -2 -1 1 1 -1

26 FM Partitioning -1 -2 -2 -2 -1 -2 -2 -1 1 1 -1

27 FM Partitioning -1 -2 -2 -2 -1 -2 -2 -2 1 -1 -1 -1

28 FM Partitioning -1 -2 -2 -2 -1 -2 -2 -2 1 -1 -1 -1

29 FM Partitioning -1 -2 -2 -2 -1 -2 -2 -2 1 -1 -1 -1

30 FM Partitioning -1 -2 -2 -2 1 -2 -2 -2 -2 1 -1 -1 -1

31 FM Partitioning -1 -2 -2 -2 1 -2 -2 -2 -2 1 -1 -1 -1

32 FM Partitioning -1 -2 -2 -2 1 -2 -2 -2 1 -2 -1 -1 -1

33 FM Partitioning -1 -2 -2 -2 1 -2 -2 -1 -2 -2 -3 -1 -1

34 FM Partitioning -1 -2 -2 1 -2 -2 -1 -2 -2 -2 -3 -1 -1

35 FM Partitioning -1 -2 -2 1 -2 -2 -1 -2 -2 -2 -3 -1 -1

36 FM Partitioning -1 -2 -2 -1 -2 -2 -2 -1 -2 -2 -2 -3 -1 -1

37 (b) Placement with 4 regions
Summary Placement Problem Minimize wirelength Subject to the non-overlapping constraint Placement Technique General flow Quadratic program based wirelength optimization FM Partitioning (a) Placement with 1 region (b) Placement with 4 regions (c) Final placements


Download ppt "EE5780 Advanced VLSI Computer-Aided Design"

Similar presentations


Ads by Google