1. December 2003 DJM DECO_021 CPU Chips & Buses

2. December 2003 DJM DECO_022 CPU Chips Modern ones are contained on a single chip Each chip has a set of pins Pins are used for communication in/out Pins have 3 functions –Address –Data –Control Connected through parallel wires called a BUS

3. December 2003 DJM DECO_023 Operational sequence FETCH - puts memory on ADDRESS BUS pins CPU control lines then set memory to READ Memory responds by putting word on DATA BUS pins Memory signals CPU when done CPU then reads the word in from DATA BUS Repeated for each word in turn

4. December 2003 DJM DECO_024 Address and Data Bus widths m address bus pins can address 2 m memory locations –m = 16, 20, 32 or 64 bits or more... n data bus pins can read/write an n bit word –n = 8, 16, 32, 36 or 64 or more... A CPU with 8 data pins will take 4 machine cycles to read a 32 bit word A CPU with 32 data pins is much faster

5. December 2003 DJM DECO_025 Other CPU pin functions Power supply –Usually 3.3 Volts or lower –A ground (0 Volt connection) A clock signal between 10MHz and 200MHz

6. December 2003 DJM DECO_026 Parallel buses in more detail... A bus is a common electrical pathway between devices Either internal to CPU or external to CPU Each type of bus is different Inside CPU designers can do what they want Outside the CPU they must use internationally recognised standards These standards specify –Mechanical plugs/sockets –Electrical voltages –Bus protocol (software rules of communication)

7. December 2003 DJM DECO_027 Multiple buses

8. December 2003 DJM DECO_028 Bus width More address bus lines mean more memory directly addressable Also means more cost on the circuit board

9. December 2003 DJM DECO_029 Bus arbitration Remember that one bus usually connects several devices Each device can both talk and listen to any other device Solutions: –Centralised or Decentralised bus arbitration Centralised e.g. –Daisy chaining - uses bus request / bus grant

10. December 2003 DJM DECO_0210 Example parallel buses Early ISA bus developed by IBM for first PCs PC/AT improved bus compatible with ISA bus –PC industry then developed their own ISA –Industry Standard Architecture bus (8.3MHz or 16.6MB/sec) –Later improved to EISA - Extended ISA (4 bytes/cycle)

11. December 2003 DJM DECO_0211 PCI bus Peripheral Component Interconnect bus (33MHz or 133MB/sec)) Developed for multimedia applications Further developed up to PCI 2.0, 2.1 and 2.2 (66MHz or 528MB/sec) –But even this is not fast enough for memory accesses –Need specially designed buses for CPU/Memory transfer

12. December 2003 DJM DECO_0212 Application of multiple buses

13. December 2003 DJM DECO_0213 Serial Buses - USB Universal Serial Bus plug nplay Relatively slow but good with peripherals Uses root hub and 2 data wires/ 2 power wires: –USB1.0 offers 1.5MB/sec (= 12Mbps) –USB2.0 offers 60 MB/sec (=480Mbps)

14. December 2003 DJM DECO_0214 Serial Buses - Firewire Standard known as IEEE 1394 Originally developed for Mac machines Similar speed to USB 2.0 but … Protocols better suited to transferring video/multimedia files –Uses isochronous transfer mode, guarantees delivery on time.