1. SoC Challenges & Transaction Level Modeling (TLM) Dr. Eng. Amr T. Abdel-Hamid ELECT 1002 Spring 2008 System-On-a-Chip Design

2. Dr. Amr Talaat ELECT1002 SoC Design Table Of Contents SoC Challenges TLM Model Concepts TLMs for different design domains

3. Dr. Amr Talaat ELECT1002 SoC Design SoC Challenges Explosive Complexity: The smaller the better Time-to-market the amount of time require d for conceiving an idea in to a real product for sales Shorter times-to-market Sky-rocketing Cost

4. Dr. Amr Talaat ELECT1002 SoC Design System Design Level

5. Dr. Amr Talaat ELECT1002 SoC Design Solutions TLM Reuse of implementations (IP Design Reuse) System standards

6. Dr. Amr Talaat ELECT1002 SoC Design Classic Design Flow Software Implementation System Level Design (Co-design Level) System Integration RTL Model Gate Model Layout Behavioral Model (Spec.) H/W Design S/W Design Algorithmic Design Architectural Design Partitioning Gate Synthesis RTL Implementation Layout Generation VHDL/Verilog Synthesis Tools

7. Dr. Amr Talaat ELECT1002 SoC Design System Description Models Transistor level HSpice, Schematic Gate level Netlist, PALASM, TEGAS RT Level HDLs

8. Dr. Amr Talaat ELECT1002 SoC Design Modern Design Flow

9. Dr. Amr Talaat ELECT1002 SoC Design Levels of Abstraction Three levels of abstraction: 1. Functional level Executable Specification Un-Timed 2. Architecture level Analyze SoC architecture Early SW development Estimated timing 3. Micro-Architecture level Pin level RTL/Behavioral HW design Exact Timing

10. Dr. Amr Talaat ELECT1002 SoC Design Transaction Level Modeling - TLM Transaction is the exchange of data or an event between two comp onent of a modeled and simulated system data can be anything from a word to a complex data structure event transaction models synchronization aspects that ensure correct operatio n of the SoC The behavior of functional blocks can be separated from communicati on The communication is described in terms of sending transactions TLM only focus on mapping out data flow details, i.e. the type of data that flows and where it is stored

11. Dr. Amr Talaat ELECT1002 SoC Design TLM – cont. RTL: The bus is wires Each device on the bus has a pin-accura te interface Each device interfac e must implement the bus protocol TLM: Bus model enforces the bus protocol Each device commu nicates via transactio n level API Less code, fewer pi ns, fewer events => much fast er

12. Dr. Amr Talaat ELECT1002 SoC Design Basics of TLM Module : structural entity, which contain processes, ports, channels, and other modules Channel : implements one or more interfaces, and serves as a container for communication functionality Port : object through which a module can access a chan nels interface. Transaction : exchange of a data or an event between tw o components of a modeled and simulated system

13. Dr. Amr Talaat ELECT1002 SoC Design Basics of TLM Hierarchical channels contain processes, ports, modules a nd channels, but primitive channels do not Primitive & Hierarchical Channel

14. Dr. Amr Talaat ELECT1002 SoC Design TLM Advantages SW development delay SW team can begin SW developi ng or testing stage much sooner HW/SW communication HW parts can communicate with SW parts in this common enviro nment. Makes the SW debug eas ier. Design space exploration Designers can decide on its part itioning (module and HW/SW par titioning) in the early stages of t he design. Simulation speed The number of events decreases

15. Dr. Amr Talaat ELECT1002 SoC Design TLM Abstraction Models Time granularity for communication/computation objects ca n be classified into 3 basic categories. Models B, C, D and E could be classified as TLMs.

16. Dr. Amr Talaat ELECT1002 SoC Design 1. Specification model 2. PE*-assembly model or Component Assembly 3. Bus-arbitration model 4. Time-accurate communication model 5. Cycle-accurate computation model 6. Implementation model TLM Abstraction Models * Processing elements

17. Dr. Amr Talaat ELECT1002 SoC Design A: Specification Model Objects -Computation -Behaviors -Communication -Variables Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Synchronization -Notify/Wait

18. Dr. Amr Talaat ELECT1002 SoC Design B: Component-Assembly Model Objects -Computation - Proc - IPs - Memories -Communication -Variable channels Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Synchronization -Notify/Wait

19. Dr. Amr Talaat ELECT1002 SoC Design C: Bus-Arbitration Model Objects -Computation - Proc - IPs (Arbiters) - Memories -Communication - Abstract bus channels Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Synchronization -Notify/Wait Bus arbiter arbitrates bus conflict

20. Dr. Amr Talaat ELECT1002 SoC Design D: Bus-Functional Model Objects -Computation - Proc - IPs (Arbiters) - Memories -Communication - Protocol bus channels Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Synchronization -Notify/Wait Time/cycle accurate communication (time constraint) Approximate timed computation Protocol channel provides functions for all abstraction bus transaction

21. Dr. Amr Talaat ELECT1002 SoC Design E: Cycle-Accurate Computation Model Objects -Computation - Proc - IPs (Arbiters) - Memories - Wrappers -Communication - Abstract bus channels Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Synchronization -Notify/Wait Modeled at register-transfer level PE are pin accurate and execute cycle-accurately Wrappers convert data transfer from higher level of abstraction to lowe r level abstraction

22. Dr. Amr Talaat ELECT1002 SoC Design F: Implementation Model Objects -Computation - Proc - IPs (Arbiters) - Memories -Communication -Buses (wires) Composition - Hierarchy - Order -Sequential -Parallel -Piped -States - Synchronization -Notify/Wait

23. Dr. Amr Talaat ELECT1002 SoC Design SOC Design Tasks 1. PE assembly and model generation Bus-arbitration model Specification model 1 PE-assembly model 2 Time-accurate Communication model 3 Implementation model 4 Cycle-accurate Computation model 5 6 78 System Design Component Design 2. Communication exploration and bus- arbitration model generation 3. Protocol refinement and time-accurate communication model generation 4. RTL/ISS* synthesis 5. IP replacement 6. Interconnect network generation 7. Accurate communication feedback 8. Accurate computation feedback * ISS : Instruction set simulator

24. Dr. Amr Talaat ELECT1002 SoC Design SOC Design Tasks 1 23 4 5 6

25. Dr. Amr Talaat ELECT1002 SoC Design Characteristics of Different Abstraction Models

26. Dr. Amr Talaat ELECT1002 SoC Design References The credit of these slides goes to: D. Gajski, L. Cai, Transaction Level Modeling: An Overview, Center for Embedded Computer Sy stems, University of California, Irvine, 2004. Z. Navabi, The Role of SystemC in theEvolution of Hardware Design, Worcester Polytechnic Inst itute. B. Vanthournout, SoC design methodology Using SystemC, Coware, 2003. F. Ghenassia, Transaction Level Modeling with SystemC: TLM Concepts and Applications for Em bedded Systems, Springer, 2005. & Others