1. CPRE 583 Reconfigurable Computing (Tools overview)
Instructor: Dr. Phillip Jones
Reconfigurable Computing Laboratory
Iowa State University
Ames, Iowa, USA

2. Outline Very basic Linux Creating a new ISE project
Running simulation from within ISE
Generating a bitfile
Downloading a bitfile to the FPGA board (impact)

3. Very basic Linux How to unpack a .zip or .tar.gz file .zip
unzip my_file.zip
.tar.gz
gunzip my_file.gz.tar
tar -xvf my_file.tar
How do I know where I am
pwd (tells you your current location, use this command often)
What is in my current location
ls (list all the files and directors at this location)
Changing directories
cd directory_name
cd .. (takes you up one directory level)
cd ~ (takes you to your home directory)
Making a new directory
mkdir new_directory_name

4. Creating a new ISE project
cd to where you want to make a directory for your project
mkdir the directory for you project
cd into the directory you made
pwd to check that you are indeed in that directory
start ise: ise &
Note: If you already have a project: ise project_name.xise &

5. Creating a new ISE project
Note you already have
a project for the AND
gate. Use these
directions to get you
going for the OR gate.

6. Creating a new ISE project

7. Creating a new ISE project
Browse to the location
of the directory you
created

8. Creating a new ISE project
Give your project a name

9. Creating a new ISE project
Make your setting match this
click Next

10. Creating a new ISE project
You project summary should look something like this. Click finish

11. Creating a new ISE project
You have no files!
Here are your choices.
Very rarely do I start a
VHDL file from scratch.
Lets create a new
source files. Then use
some existing VHDL to
fill it.
For example for the OR
gate. Add new source files
for the testbench and
OR gate. Then copy/paste
from the given AND example
to get you going.

12. Creating a new ISE project
Right click to pop up options

13. Creating a new ISE project
Indicate you are
Adding a VHDL
file
In this case we will add two source files. One for the testbench (AND_TB) to
test the AND gate (AND_2bit).

14. Creating a new ISE project
You can add the port names, direction and width here. Since we are going
to copy VHDL source code form somewhere else we will skip this step.
Note: This is a step for convince for when you do not have code to start from.

15. Creating a new ISE project

16. Creating a new ISE project
The tool tries to be helpful by adding some VHDL for you. I would suggest
deleting this and copying from the AND gate example, until you get
more comfortable with the tools.

17. Creating a new ISE project
Now let’s add a source file for the 2-bit AND gate component.

18. Creating a new ISE project

19. Creating a new ISE project

20. Creating a new ISE project

21. Creating a new ISE project
You have some files
Note: The Hierarchy window should show the strutural relationship between
your files. At this point it shows AND_TB and AND_2bit at the same level

22. Creating a new ISE project
The 2-bit AND gate is
a subcomponent of
AND_TB.
After updating your VHDL files with the appropriating “entity” and
“component” names. ISE will figure out the hierarchy.

23. Creating a new ISE project
If you see a question mark,
this could mean ISE lost
track of your file when you
were editing it.
If your file is indeed in the
project directory, then just
tell ISE

24. Creating a new ISE project
Remind ISE where it is
Note: The “?” can also appear if you incorrectly named you entity in the VHDL

25. Creating a new ISE project

26. Simulating your design
Set “View” to Simulation
Select at what level you
want to compile or
simulate. In this case
the whole design

27. Simulating your design
Set simulation properties.
For example how long to
run for

28. Simulating your design
For this case I’ve set the simulation to run for 1000 ns

29. Simulating your design
Now simulate

30. Simulating your design
Modelsim compiles your
VHDL before simulating it. In this case it caught a
syntax error.
Missing semicolon

31. Simulating your design
It looks like this version of ISE does syntax checking every time you
save a file. So this error could have been caught earlier.

32. Simulating your design
Now that you can run simulation. You need to add signals and dividers.
Right click in the “Wave” window to Insert a Divider

33. Simulating your design2 3 1
To add signals for the AND gate. 1) select it in “Instance”, this instance of the
AND gate is called “my_dut”, 2) select the signals in the “Objects window,
3) Drag and drop the signals into the “Wave” window

34. Simulating your design
Typically you will want ALL of your signal in “Hexadecimal”. To do this
1) select all of the signals, 2) right in wave window, 3) Radix->Hexadecimal

35. Simulating your design: Saving wave formats
To keep from having to reformat you signals EVERY time for the same
Design, save you wave format

36. Simulating your design: Saving wave formats
For this project I have named the wave format HW1_3_a_AND_wave.do
Next we will look at how to tell ISE to use this wave format when it launches Modelsim.
Note: there are a number of ways of doing this, and even different versions
of ISE support different methods. Often this is something you need to play around with and figure out yourself.

37. Simulating your design: Saving wave formats
ISE file that will call your wave format
Contents of your project directory
Wave format you
just created
“cat” prints the contents of a file
This is how I modified
AND_TB_wave.fdo
Tell ISE to only call your wave format file
After you make this updates, restart Modelsim from ISE to see if it worked

38. Simulating your design: Saving datasets
Some times you want to save the dataset (.wlf) for a simulation run. Often this is used to compare the behavior of one version of a design to another while debugging. And for this class you will save datasets so that I can review the behavior of your circuits without needed your source code.

39. Simulating your design: Saving datasets
1. Modelsim typically saves the current dataset as “vsim.wlf”
2. Rename it to the name you want. In this case HW1_2_a_AND_dat.wlf

40. Simulating your design: Loading Dataset
To check if your dataset saved correctly open Modelsim standalone (vsim &), and load the wave dataset (.wlf), and then the associated wave format

41. Simulating your design: Loading Datasets
Open a wave window, then readjust/resize the windows of Modelsim

42. Simulating your design: Loading Datasets
Find and open the dataset

43. Simulating your design: Loading Datasets2 6 5 1 2 4
Find and open the dataset

44. Simulating your design: Loading Datasets
Now load the wave format (.do) associated with this dataset

45. Simulating your design: Loading Datasets
Browse to find the correct wave format (.do)

46. Simulating your design: Loading Datasets
Your dataset and associated waveform should appear

47. Simulating your design: Useful Buttons
Zoom mode (VERY useful!!)
Zoom out
Jump to previous or next signal
value transition (VERY useful!!)
Select mode
Zoom in
Zoom full
Toggle between short
and full signal names
Useful Buttons in Modelsim

48. Generating a bitfile
View can be set to simulation or Implementation. Implementation
only shows those files that will go on the hardware. Simulation typically shows files that will be simulated and/or put on the hardware

49. Generating a bitfile
Any source file that will only be simulated should have its properties set to reflect this. In this case AND_TB will be set to Simulation. And my_dut (AND_2bit) will be set to ALL (i.e. both simulation and implementation)

50. Generating a bitfile
Any source file that will only be simulated should have its properties set to reflect this. In this case AND_TB will be set to Simulation. And my_dut (AND_2bit) will be set to ALL (i.e. both simulation and implementation)

51. Generating a bitfile
Now when the view is switch to “Implementation” only VHDL that will be put
on the hardware is shown. Also note in the “Processes” we have new options. One of which is “Generate Programming File”

52. Generating a bitfile
One typically selects the top level component and runs “Generate Programming File” to generate a bitfile to download to the FPGA. Note we’ve switched to MP1 because the AND_2bit example does not have a user constraint file (.ucf) defined to tell the tools how to connect the design to the FPGA I/O pins

53. Generating a bitfile
If all goes well, then after some time you should get a GREEN check next the “Generate Programming File”. And a file called <top_level>.bit, in this case MP1_top.bit, should be placed in your project directory.

54. Downloading a bitfile to the FPGA
Go to the directory where your bitfile is located and start impact
Note: You must be on a machine that has an FPGA board connected to it.

55. Downloading a bitfile to the FPGA
Yes should be fine as well

56. Downloading a bitfile to the FPGA

57. Downloading a bitfile to the FPGA

58. Downloading a bitfile to the FPGA
Bypass until you
get to the FX70

59. Downloading a bitfile to the FPGA
FX 70 is now
selected (GREEN)

60. Downloading a bitfile to the FPGA

61. Downloading a bitfile to the FPGA

62. Downloading a bitfile to the FPGA

63. Downloading a bitfile to the FPGA

64. Generating a bitfile: Fixing a locked cable
For various reasons “impact” will have an issue downloading your bitfile. This can be caused by more than one person trying to run impact to connect to the board, or impact crashing, or power being turned off to the board.
In the worst case one as to reboot the machine. We like to avoid this because you do not have administrative rights to reboot the machine. Though one campus students can power cycle.
Some things to try
In impact: output -> cable reset
From the command line
> impact -batch
> setMode -bscan
> cleancablelock
> quit
> xmd
> xclean_cablelock
Send me an , and/or a “wall” message