1. Nanofabrication Facilities at TIFR and IIT-B
Venu Gopal Achanta Department of Condensed Matter Physics and Material Sciences Tata Institute of Fundamental Research

2. Outline
Various facilities available at TIFR and IIT,B to carry out each process step
Some examples briefly
Preliminary results related to SiPM
SiN deposition for AR coating
Poly Silicon resistors
Si etching for isolation
Summary

3. Nanofabrication Two approaches to nanofabrication
Bottom-up  building walls, brick by brick
Top down  chiseling sculptures from stone
Challenges in bottom-up
Placing nanomaterials where we need
Require a cleanroom
Yellow light, suits, air shower, sticky mats, HEPA filters, positive pressure, smooth corners

4. Cleanroom Classification
maximum particles/m3
FED STD 209E equivalent
>=0.1 µm
>=0.2 µm
>=0.3 µm
>=0.5 µm
>=1 µm
>=5 µm
ISO 1 10 2
ISO 2
100 24 4
ISO 3
1,000
237
102 35 8
Class 1
ISO 4
10,000
2,370
1,020
352 83
Class 10
ISO 5
100,000
23,700
10,200
3,520
832 29
Class 100
ISO 6
1,000,000
237,000
102,000
35,200
8,320
293
Class 1,000
ISO 7
352,000
83,200
2,930
Class 10,000
ISO 8
3,520,000
832,000
29,300
Class 100,000
ISO 9
35,200,000
8,320,000
293,000
Room Air

5. Nanofabrication process steps

6. TIFR class 1000 cleanroom
Sputter system
Tools for deposition, patterning, pattern transfer and characterizing
Mask Aligner
RIE
CVD
EBL
ALD

7. Substrate Preparation Tools
Wet bench + Hot plates
RCA cleaning – 4 steps
Organic clean, Oxide strip
ionic cleaning, rinsing and drying
5 parts of deionized water
1 part of aqueous NH4OH (ammonium hydroxide, 29% by weight of NH3)
1 part of aqueous H2O2 (hydrogen peroxide, 30%)
at 75 or 80 °C[1] typically for 10 minutes. This base-peroxide mixture removes organic residues. Particles are also very effectively removed, even insoluble particles, since SC-1 modifies the surface and particle zeta potentials and causes them to repel.[4] This treatment results in the formation of a thin silicon dioxide layer (about 10 Angstrom) on the silicon surface, along with a certain degree of metallic contamination (notably Iron) that shall be removed in subsequent steps.
Second step (optional): oxide strip[edit]
The optional second step (for bare silicon wafers) is a short immersion in a 1:100 or 1:50 solution of HF + H2O at 25 °C for about fifteen seconds, in order to remove the thin oxide layer and some fraction of ionic contaminants. If this step is performed without ultra high purity materials, it can lead to recontamination since the bare silicon surface is very reactive.[2]
Third step (SC-2): ionic clean[edit]
The third and last step (called SC-2) is performed with a solution of[2]
1 part of aqueous HCl (hydrochloric acid, 39% by weight)
at 75 or 80 °C, typically for 10 minutes. This treatment effectively removes the remaining traces of metallic (ionic) contaminants, some of which were introduced in the SC-1 cleaning step.[1] It also leaves a thin passivating layer on the wafer surface, which protects the surface from subsequent contamination (bare exposed silicon is contaminated immediately).[2]
Fourth step: rinsing and drying[edit]
Provided the RCA clean is performed with high-purity chemicals and clean glassware, it results in a very clean wafer surface while the wafer is still submersed in water. However, if the rinsing and drying steps are not performed correctly then the surface becomes easily recontaminated with organics and particulates floating on the surface of water. A variety of procedures can be used to rinse and dry the wafer effectively.[2]

8. Deposition Tools Spin coater Sputtering system
Thermal & e-beam evaporator
ICP-Chemical Vapor Deposition
SiO2, Si3N4
Atomic Layer Deposition
TiO2, Al2O3, HfO2, Pt
Hot wire CVD (IIT)
SiN, intrinsic or p-doped poly Si
Pulse laser deposition
Rapid thermal annealer
Boron doped polysilicon

9. Patterning Tools Photolithography Electron beam lithography
~ 2m resolution
Electron beam lithography
~ 15nm resolution
Holographic interferometry
~50nm resolution

10. Pattern transfer tools
Inductively coupled Reactive Ion Etcher
Dielectrics
Metals as well
Wet bench
Chemical etching
BCl3, Cl2, Ar, SF6 and O2 (process gases)

11. Mask Maker (IIT) Standard Photolithography requires Masks
Laser Writer with 405nm (GaN) or 325nm (He-Cd) lines
0.7µm resolution
100x100mm or 400x400mm area
Chrome or Iron Oxide plated

12. Electrical/Electronic tools
Wire bonder
Probe stations
Room temperature
Low temperature

13. Characterization Tools
Microscopy tools
Optical microscope
Profilometer
Atomic Force Microscope
Scanning Electron Microscope
Transmission Electron Microscope
Spectroscopy tools
Photoluminescence
Raman spectrometer
X-ray Diffractometer
UV-Visible spectrometer
Fourier transform infrared spectrometer (FTIR)

14. Some related results Results with IIT-TIFR collaboration
Photolithography
Electron beam lithography
Interference lithography
IIT-TIFR collaboration
Amorphous Silicon deposition and annealing
Fabrication of silicon micro-resistors

15. Nanophotonics : Our Lab
QD Spin-Photon Converter: Phy. Rev. Lett
Reflectionless Potential: Opt. Expr
3 µm
Plasmonic Quasi Crystal: Sci. Rep
VIS-NIR Metamaterial:
Dual band DEMUX J. Appl. Phys.
Plasmonic Crystal:
Nature Comm.

16. THz Spectroscopy: Prof. S. S. Prabhu’s Lab
Novel THz Sources:
APL, AIP Adv.
THz Metamaterial: Multiband Polarizers
Angle Tunable resonances
Pressure : 5Pa
cw THz Source: J. Appl. Phys.
Broadband THz Filter

17. Antireflection coating
Several ways to realize anti-reflection coating
Effective layer with refractive index n=sqrt(n1*n2)
Multilayer stack like quarter wave stack to destructively cancel the reflections
Multilayer stack to have adiabatic change in refractive index from air to substrate
Biomimetic designs
Patterning substrates
Single layer AR coatings are more popular as they are cost effective

18. SiN CVD deposition for AR
SiH4 150sccm + NH3 8.5sccm + Ar 150sccm
Chamber Pressure : 5Pa
Substrate Temp : 130C
ICP Power : 500W
Rate : ~25nm/min
Thickness of SiN required is ~100nm

19. Poly-silicon film growth with HWCVD
In-situ boron doped poly-si film is deposited using Hot Wire CVD, available at IIT Bombay, Mumbai
Film has been optimized with various deposition parameters such substrate temperature, boron doping for desired resistivity
Developed films are characterized by X-ray diffraction to check crystalinity
Doping profile along the thickness is measured using SIMS (Secondary Ion Mass Spectroscopy)
Hot-Wire CVD
SIMS Results

20. Patterning of the poly-si
Resistors are patterned with optical (U.V) lithography
Plasma assisted reactive ion etching used
PECVD used for deposition of SiO2 layer for passivation.
Total process involves three masks and thus accurate alignment between subsequent lithography steps
Masks designed at TIFR and fabricated at IITB
Mask aligner
ICP- RIE Plasma Etcher
Fabricated resistors

21. Contact Annealing and Characterization
A short Rapid Thermal cycle is used to anneal the Aluminum contacts
Final sample is characterized using a probe station
I-V characteristics of many resistors is recorded
(more than 100)
Overall 7% variation is seen across the sample
Major part of the variation is due to non-uniformity in films
Characterization
Before Annealing
Resistance Distribution
After Annealing

22. Trenches in Si
Silicon etching with ICP-RIE tried to get the required deep trenches
1-2m deep trenches made with ICP-RIE
Filling them with polymer and polishing required.
BEL has been approached to test the process steps and for further manufacturing
1.57 µm
I will add some AFM/SEM images of trenches made in Si by ICP-RIE

23. Summary Fabrication steps are being tested in-house where possible
Si etching for trenches
SiN deposition for AR coatings
Masks for lithography
Polysilicon resistors
Alternate fabrication process that does not involve implantation is being studied
Final process is to be transferred to foundry