1. Computer Science Education
ARM CPU Internal I
Prof. Taeweon Suh
Computer Science Education
Korea University

2. Overview
For the sake of your understanding, we simplify the CPU and its system structure
CPU
North Bridge
South Bridge
Main Memory
(DDR)
FSB
(Front-Side Bus)
DMI
(Direct Media I/F)
Real-PC system
Memory
(Instruction, data)
ARM CPU
Address Bus
Data Bus
Simplified

3. Actual ARM Connection
ARM CPU has separate connections to memory (caches)
ARM920T
Memory
Instruction fetch
Instruction
Cache
Address Bus
Data Bus
ARM CPU core
Address Bus
Address Bus
Data Bus
Data
Cache
Data Bus
Instruction/
Data access
Data access

4. Overview Microarchitecture is composed of datapath and control
Datapath operates on words of data
Datapath elements are used to operate on or hold data within a processor
Datapath elements include the register file, ALU, muxes, and memory
Control tells the datapath how to execute instructions
Control unit receives the current instruction from the datapath and tells the datapath how to execute that instruction
Specifically, the control unit produces mux select, register enable, ALU control, and memory write signals to control the operation of the datapath
Essential ARM instructions
Data processing instructions: add, sub, cmp, and, or
Memory access instructions: ldr, str
Branch instructions: b, bl

5. Instruction Execution in CPU
Generic steps of the instruction execution in CPU
Fetch uses the program counter (PC) to supply the instruction address and fetch instruction from memory
Decoding decodes instruction and reads operands
Extract opcode: determine what operation should be done
Extract operands: register numbers or immediate from fetched instruction
Execution
Use ALU to calculate (depending on instruction class)
Arithmetic or logical result
Memory address for load/store
Branch target address
Access memory for load/store
Next Fetch
PC  target address or PC + 4
Address Bus
Instruction/
Data
Memory
ARM CPU core
Fetch with PC
Data Bus
PC = PC +4
Decode
Address Bus
Execute
Data Bus

6. Increment by 4 for the next instruction 32-bit register (flip-flops)
Instruction Fetch
ARM CPU core
Increment by 4 for the next instruction 4
Add
Memory
Address
Out 32 PC
reset
clock
instruction
32-bit register (flip-flops)
What is PC on reset in ARM?
PC = 0x0000_0000

7. Memory
Memory is classified into RAM (Random Access Memory) and ROM (Read-Only Memory)
RAM is classified into DRAM (Dynamic RAM) and SRAM (Static RAM)
DDR is a kind of DRAM
DDR is a short form of DDR (Double Data Rate) SDRAM (Synchronous DRAM)
DDR is used as main memory in modern computers

8. Simple ARM Test Code
assemble

9. Instruction Decoding
Instruction decoding separates the fetched instruction into the fields
Opcode determines which operation the instruction wants to do
Control logic should be designed to supply control signals to datapath elements (such as ALU and register file)
Operands
Register numbers in the instruction are sent to the register file
Immediate field is either sign-extended or zero-extended depending on instructions*
*It seems immediate is zero-extended in ARM case. If you write “add r1, r2, #-12”, assembler generates “sub r1, r2, 12”. The shifter operand could be “logical (or arithmetic) shift right a register by immediate. In this case, the register is zero-filled or signed-filled in the shifted vacant bits

10. Schematic with Instruction Decoding
ARM CPU
Control Unit
Opcode
RegWrite
Register File
Inst[15:12] (=Rd)
Inst[19:16] (=Rn)
Inst [3:0] (=Rm) Rn 32 Rm wd
RegWrite R0 R1 R2 R3
R14
R15 (PC) …
instruction PC
Add 4
reset
clock
Memory
Address
Out 8 32
zero-extended
imm 32

11. Instruction Execution #1
Arithmetic and logical instructions
Examples: add, adc, sub, sbc, cmp, mov, and, or …
Two source operands
One is always a register
The other has two basic forms: Immediate or register (optionally shifted)
add r1, r2, r3 # r1 = r2 + r3
add opcode: 0100
sub r1, r2, r3 # r1 = r2 – r3
sub opcode: 0010

12. Data Processing Instruction Formats
Source: ARM Architecture Reference Manual

13. Schematic with Instruction Execution #1
ARM CPU
Control Unit
opcode
ALUSrc
RegWrite
Register File
Inst[15:12] (=Rd)
Inst[19:16] (=Rn)
Inst [3:0] (=Rm) Rn 32 Rm wd
RegWrite R0 R1 R2 R3
R14
R15 (PC) …
ALU
ALUSrc
instruction
mux PC
Add 4
reset
clock
Memory
Address
Out 8 32
zero-extended
imm 32

14. Instruction Execution #2
Memory access instructions
ldr, str instructions
ldr R1, [R2, #4] // R1 <= [R2 + 4]
str R1, [R2,R3] // [R2 + R3] <= R1

15. Memory Access Instruction Formats
Load and Store Word or Unsigned Byte instructions
* 12-bit immediate is for load and store word or unsigned byte.
* 8-bit immediate is used for halfword and signed byte instructions
Source: ARM Architecture Reference Manual

16. Schematic with Instruction Execution #2
ARM CPU
Control Unit
opcode
MemWrite
MemtoReg
8-or-12
Memory
Address
ReadData
WriteData
MemWrite
ALUSrc
RegWrite
Register File
Inst[15:12] (=Rd)
Inst[19:16] (=Rn)
Inst [3:0] (=Rm) Rn 32 Rm wd R0 R1 R2 R3
R30
R31 … Rd
ALU
ALUSrc
instruction
mux
MemtoReg
Prof. Suh’ note: For store to work, register file has to have another port (read port). The read port input should be multiplexed with Rs and Rd.
mux
8-or-12 PC
Add 4
reset
clock
Memory
Address
Out 8 32
zero-extended
imm 32 12
ldr R1, [R2, #4] // R1 <= [R2 + 4]
str R1, [R2, R3] // [R2 + R3] <= R1

17. Instruction Execution #3
Execution of the branch and jump instructions
b, bl instructions
b target (offset)
Destination = (PC + 8) + sign-extend (imm << 2)

18. Schematic with Instruction Execution #3 (B)
ARM CPU
Control Unit
opcode
branch
Memory
Address
ReadData
WriteData
MemWrite
Register File
Inst[15:12] (=Rd)
Inst[19:16] (=Rn)
Inst [3:0] (=Rm) Rn 32 Rm wd R0 R1 R2 R3
R14
R15 (PC) … Rd
ALU
ALUSrc
mux
MemtoReg
instruction
mux
8-or-12
branch 12 32
zero-extended
imm
mux
Add
Memory
Address
Out 4
Add 24
imm
Sign extension
<<2 32 PC 32
reset
clock
Note that Branch Destination = (PC+8) + (sign-extend) (imm << 2)}