1. Thermal Model Feedback
Rev 01
5/17/2017
Yueming Li, Thermal Engineer, Facebook
John Fernandes, Thermal Engineer, Facebook
Jia Ning, Hardware Engineer, Facebook

2. Feedbacks from Last Meeting
Include the power stage especially for the hot-aisle cases
Add 750 LFM for the hot-aisle cases for analysis
Add heat sink cutout for all hot-aisle cases
Provide equal priority to hot-aisle configurations
Add 750 LFM for only hot-aisle simulations
ASIC power ≥ 25W should include DRAM chips as well
Mellanox – Using a simple block with an embedded heat source will provide very optimistic simulation results. Mellanox has a detailed model of a QSFP module.
Can NIC vendors provide input on expected ASIC power consumption under standby mode?
[Bergi/intel] For full standby functionality with optics, the power will be roughly half of the Max power.
Quad SFP cage simulation at some point

3. Comments Needed Simplistic modeling of QSFP modules
PCB model
Simplistic modeling of QSFP modules
NIC PCB was modeled with layer definition
ASIC uses a 2-resistor model
DRAM uses a 2-resistor model
It might not be possible to fit 8 DRAM chips on board size 7a.
What is the minimum acceptable quantity of DRAM chips on board size 7a?
[Bergi/Intel] The minimum acceptable quantity of DRAM chips on board size 7a is zero, since this size board would be used for simpler/basic, lower end designs.
As Jia highlighted during the meeting, if NIC vendors have any data or correlations that can help increase the accuracy of the models, sharing this information would be helpful.
ASIC model
DRAM model

4. Updated Thermal Cases