1. Digital Computer Fundamentals
System Buses
Mukesh N. Tekwani
Mumbai, India

2. All the units must be connected
Connecting
All the units must be connected
Different type of connection for different type of unit
Memory
Input/Output
CPU

3. Computer Modules

4. Receives and sends data Receives addresses (of locations)
Memory Connection
Receives and sends data
Receives addresses (of locations)
Receives control signals
Read
Write
Timing

5. Input/Output Connection(1)
Similar to memory from computer’s viewpoint
Output
Receive data from computer
Send data to peripheral
Input
Receive data from peripheral
Send data to computer

6. Input/Output Connection(2)
Receive control signals from computer
Send control signals to peripherals
e.g. spin disk
Receive addresses from computer
e.g. port number to identify peripheral
Send interrupt signals (control)

7. CPU Connection
Reads instruction and data
Writes out data (after processing)
Sends control signals to other units
Receives (& acts on) interrupts

8. What is a Bus?
A communication pathway connecting two or more devices
It is a shared transmission medium
A signal transmitted by one device can also be received by other devices on the same bus
Only one device can transmit at a time
A bus consists of many transmission lines. Each line can transmit a binary 1 or 0.
In a computer system a bus that connects the processor, memory and I/O is called the system bus

9. Bus Types
Data Bus
Address Bus
Control Lines

10. The number of lines is called “width” of the data bus
Carries data
Remember that there is no difference between “data” and “instruction” at this level
The number of lines is called “width” of the data bus
Width is an important factor in determining the system performance

11. Identify the source or destination of data
Address bus
Identify the source or destination of data
e.g. CPU needs to read an instruction (data) from a given location in memory
Bus width determines maximum memory capacity of system
e.g has 16 bit address bus giving 64k address space

12. Control lines consist of:
Control Bus
Control lines consist of:
Memory write / memory read
I/O write / I/O read
Bus request (to indicate that a module needs control of the bus)
Interrupt request (to indicate that an interrupt is pending)
Interrupt ACK (to acknowledge that interrupt has been recognized)
Reset ( to reset all modules)
Clock (to synchronize all operations)

13. Bus Interconnection Scheme

14. Big and Yellow? What do buses look like?
Parallel lines on circuit boards
Ribbon cables
Strip connectors on mother boards
e.g. PCI
Sets of wires

15. Physical Realization of Bus Architecture

16. Lots of devices on one bus leads to:
Single Bus Problems
Lots of devices on one bus leads to:
Propagation delays
More devices attached to the bus mean more is the propagation delay
Most systems use multiple buses to overcome these problems

17. Traditional Bus Architecture

18. High Performance Bus

19. Bus Types Dedicated Multiplexed Separate data & address lines
Dedicated bus line is permanently assigned to a set of components
Some computer systems have a dedicated address and data bus
Multiplexed
Shared lines
Address valid or data valid control line
Advantage - fewer lines, saving space & cost
Disadvantages
More complex circuits
Certain events cannot take place in parallel

20. Co-ordination of events on bus Synchronous
Timing
Co-ordination of events on bus
Synchronous
Events determined by clock signals
Control Bus includes clock line
A single 1-0 is a bus cycle
All devices can read clock line
Usually sync on leading edge
Usually a single cycle for an event

21. Peripheral Component Interconnect
PCI Bus
Peripheral Component Interconnect
It is a high bandwidth, processor independent bus
32 or 64 bit
50 lines

22. PCI Bus Lines (required)
Systems lines
Including clock and reset
Address & Data
32 time mux lines for address/data
Interrupt & validate lines
Interface Control – control timing of transactions
Error lines – used to report parity and other errors

23. PCI Bus Lines (Optional)
Interrupt lines
Not shared
Cache support
64-bit Bus Extension
Additional 32 lines
Time multiplexed
2 lines to enable devices to agree to use 64-bit transfer

24. Transaction between initiator (master) and target Master claims bus
PCI Commands
Transaction between initiator (master) and target
Master claims bus
Determine type of transaction
e.g. I/O read/write
Address phase
One or more data phases

25. Thank You