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Multi-level Coarsening Algorithm
Perform Edge Coarsening (EC) Visit nodes and break ties in alphabetical order Explicit clique-based graph model is not necessary Practical Problems in VLSI Physical Design
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Edge Coarsening Practical Problems in VLSI Physical Design
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Edge Coarsening (cont)
Practical Problems in VLSI Physical Design
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Obtaining Clustered-level Netlist
# of nodes/hyperedges reduced: 4 nodes, 5 hyperedges Practical Problems in VLSI Physical Design
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Hyperedge Coarsening Initial setup
Sort hyper-edges in increasing size: n4, n5, n1, n2, n3, n6 Unmark all nodes Practical Problems in VLSI Physical Design
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Hyperedge Coarsening Practical Problems in VLSI Physical Design
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Hyperedge Coarsening Practical Problems in VLSI Physical Design
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Obtaining Clustered-level Netlist
# of nodes/hyperedges reduced: 6 nodes, 4 hyperedges Practical Problems in VLSI Physical Design
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Modified Hyperedge Coarsening
Revisit skipped nets during hyperedge coarsening We skipped n1, n2, n3, n6 Coarsen un-coarsened nodes in each net Practical Problems in VLSI Physical Design
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Modified Hyperedge Coarsening
Practical Problems in VLSI Physical Design
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Obtaining Clustered-level Netlist
# of nodes/hyperedges reduced: 5 nodes, 4 hyperedges Practical Problems in VLSI Physical Design
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