1. SoCks Hardware / Software Codesign Andrew Pearson Sanders DeNardi ECE6502 May 4, 2010

2. What is SoCks? Implements an open source SPARC V8 SoC with custom memory-mapped functionality. SoCks is a LEON core, a collection of BASH scripts, C code, and HDL.

3. LEON Core

4. SoCks SoC Simulation Testbench AHB Bus Leon AHB Controller Memory Controller Sparc CPU Custom Logic AHB Slave Interface External Memory RAM/ROM IO Monitor: Text Output File Output Clock/ Reset Generator SOCks ASIC

5. Why Hardware Acceleration? Implement software in hardware – Faster – Better Parallelism Why Use SoCks? Simplifies design process Easy to test Platform approach

6. Design Flow Custom HDL Implementing Software Cadence IUS 8.2 (ncvhdl, ncvlog, ncelab) LEON and RAM HDL C Firmware SPARC RTEMS GCC C Compiler Simvision

7. Initial Hurdles Trying to port scripts to Cadence RC (RTL Compiler) Compiling C in correct environment Getting proper version of IUS 8.2

8. Our Custom HDL What should we try to implement? – Initially wanted to do encryption or decoding (MD5, SHA1, MP3, JPEG) Would spend more time working on Verilog than on the intricacies of hardware-accelerated SoCs – Decided on Greatest Common Divisor acceleration Non-determinate amount of steps in algorithm Requires repeated subtraction (inefficient)

9. Our Custom HDL (cont.) Euclids algorithm for GCD Implemented in Verilog Implemented in C Compared execution time

10. Our Algorithm Numbers X and Y X>Y? YESNO X=X-YY=Y-X Y==0? DONE YES NO

11. An Interesting Problem… int nums[10]={20,40,10,3,4,5,39,40,41,42};... for(j=0;j<10;j++) { custom[0]=nums[j]; custom[1]=10; custom[2]=1; print_int(nums[j]); print_int(custom[2]); }...

12. An Interesting Problem… (cont.) 1st 2nd 3rd

13. An Interesting Problem… (cont.) Why? CC=sparc-rtems-gcc CFLAGS= -O2 -g LDFLAGS=-g -N -nostdlib -T./linkleon -e _hardreset locore1.o LIBS=-L/opt/rtems/sparc-rtems/lib -lgcc -lm...

14. Solution Optimization flag should NOT be on! You are writing firmware / device driver – The compiler should NOT be changing your code – Best practice to write in assembly code, not C

15. Results Execution of non-accelerated code: – 19,561 ns Execution of accelerated code: – 8,612 ns Thats 227% faster!

16. Lessons Learned Hardware optimization really works SoCks requires many configuration changes before it can work at UVa – Should be updated to run on newer tools State of Cadence software Relying on compilers for firmware/drivers

17. Questions?