1. Recall Last Lecture The MOSFET has only one current, ID
Operation of MOSFET
NMOS and PMOS
For NMOS,
VGS > VTN
VDS sat = VGS – VTN
For PMOS
VSG > |VTP|
VSD sat = VSG + VTP

2. ID versus VDS (NMOS) or ID versus VSD (PMOS)

3. PMOS NMOS VTP is NEGATIVE VTN is POSITIVE VSG > |VTP| to turn on
Triode/non-saturation region
Saturation region
VSDsat = VSG + VTP
NMOS
VTN is POSITIVE
VGS > VTN to turn on
Triode/non-saturation region
Saturation region
VDSsat = VGS - VTN

4. DC analysis of FET

5. MOSFET DC Circuit Analysis - NMOS
The source terminal is at ground and common to both input and output portions of the circuit.
The CC acts as an open circuit to dc but it allows the signal voltage to the gate of the MOSFET.
In the DC equivalent circuit, the gate current into the transistor is zero, the voltage at the gate is given by a voltage divider principle:
VG = VTH = R2 VDD
R1 + R2
Use KVL at GS loop:
VGS –VTH + 0 = 0
VGS = VTH

6. MOSFET DC Circuit Analysis - NMOS
Assume the transistor is biased in the saturation region, the drain current:
Use KVL at DS loop
IDRD + VDS – VDD = 0
If VDS > VDS(sat) = VGS – VTN, then the transistor is biased in the saturation region.
If VDS < VDS(sat), then the transistor is biased in the nonsaturation region.

7. EXAMPLE:
Calculate the drain current and drain to source voltage of a common source circuit with an n-channel enhancement mode MOSFET. Assume that R1 = 30 k, R2 = 20 k, RD = 20 k, VDD = 5V, VTN = 1V and Kn = 0.1 mA/V2
VTH = = 2V hence VGS = VTH = 2V
VDSsat = VGS – VTN = 2 – 1 = 1V, so, VDS > VDSsat, our assumption that the transistor is in saturation region is correct

8. EXAMPLE The transistor has parameters VTN = 2V and Kn = 0.25mA/V2.
VDD = 10V
The transistor has parameters VTN = 2V and Kn = 0.25mA/V2.
Find ID and VDS
RD = 10k
R1 = 280k
R2 = 160k

9. Solution
1. VTH = = V
KVL at GS loop: VGS – VTH + 0 = 0  VGS = VTH
2. Assume in saturation mode: ID = Kn(VGS - VTN)2 So, ID = mA 3. KVL at DS loop: VDS = VDD – IDRD = 10 – (10) = 3.31 V 4. VDS sat = VGS – VTN = – 2 = V So, VDS > VDSsat , therefore, assumption is correct!
Answer: ID = mA and VDS = 3.31 V

10. MOSFET DC Circuit Analysis - PMOS
Different notation:
VSG and VSD
Threshold Voltage = VTP
VG = VTH = R2 VDD
R1 + R2
Use KVL at GS loop:
VSG VTH – VDD = 0
VSG = VDD - VTH

11. MOSFET DC Circuit Analysis - PMOS
Assume the transistor is biased in the saturation region, the drain current:
Calculate VSD:
Use KVL at DS loop:
VSD + IDRD - VDD = 0
ID = Kp (VSG + VTP)2
VSD = VDD - IDRD
If VSD > VSD(sat) = VSG + VTP, then the transistor is biased in the saturation region.
If VSD < VSD(sat), then the transistor is biased in the non-saturation region.

12. Calculate the drain current and source to drain voltage of a common source circuit with an p-channel enhancement mode MOSFET.
Also find the power dissipation.
Assume that, VTP = -1.1V and Kp = 0.3 mA/V2 5V
Use KVL at SG loop:
VSG – 5 = 0
VSG = 5 – 2.5 = 2.5 V
Assume biased in saturation mode:
Hence, ID = 0.3 ( 2.5 – 1.1)2 = mA
Calculate VSD
Use KVL at SD loop:
VSD + IDRD – 5 = 0
VSD = 5 - IDRD
VSD = 5 – ( 7.5) = V
50 k
VSG > |VTP |
50 k
7.5 k

13. VSD sat = VSG + VTP = 2.5 – 1.1 = 1.4V
Hence, VSD < VSD sat. Therefore assumption is incorrect. The transistor is in non-saturation mode!
ID = ( 2.5 – 1.1) (5 – IDRD) – (5 – IDRD)2
ID = (5 – 7.5ID) – (5-7.5ID)2
ID = – 21ID – (25 – 75ID ID2)
ID = – 21ID ID – 56.25ID2
56.25 ID2 – ID + 11 = 0
ID = mA
ID = mA

14. ID = mA
ID = mA
VSD = 5 – IDRD = 0.98 V
VSD = 5 – IDRD = 2.26 V
VSD sat = VSG + VTP = 2.5 – 1.1 = 1.4V
0.98V < 1.4V
Smaller than VSD sat : OK!
2.26V > 1.4V
Bigger than VSD sat : not OK
Answer: ID = mA and VSD = 0.98V
Power dissipation = ID x VSD = mW

15. LOAD LINE Common source configuration i.e source is grounded.
It is the linear equation of ID versus VDS
Use KVL
VDS = VDD – IDRD
ID = -VDS + VDD RD RD

16. ID (mA)
VDS (V)
VGS
VDS ID
Q-POINTS
y-intercept
x-intercept

17. DC Analysis where source is NOT GROUNDED
For the NMOS transistor in the circuit below, the parameters are VTN = 1V and Kn = 0.5 mA/V2.

18. b) Write down the branch current equation for the source terminal.
What is the value of VG ?
b) Write down the branch current equation for the source terminal.
c) Get an expression for VGS in terms of ID
VG = -1V ID
VS – (-5) = ID 1
VS = ID
use KVL:
0 + VGS+ 1(ID) = 0
VGS = 4 - ID
Or use node voltages: VGS = VG - VS
VGS = -1 – ( ID – 5)
VGS = 4 - ID

19. d) The transistor is biased in saturation mode, calculate ID
d) The transistor is biased in saturation mode, calculate ID. You will know which value of ID that you need to choose by calculating VGS. Justify your answer. ID

20. ID
e) Write down the branch current equation for the drain terminal
f) Calculate VDS and confirm that the transistor is biased in saturation mode.
5 - VD = ID 2
VD = 5 - 2ID
Use KVL:
IDRD + VDS + IDRS – 5 – 5 = 0
1.354 (2) + VDS – 10 = 0
VDS = 10 – – = V
Or use node voltages:
VDS = VD - VS
where VD = ( 1.354) = V
And VS = ID - 5 = V
So, VDS = – (-3.646) = V
VDS sat = VGS – VTN = – 1 = V
VDS > VDS sat  CONFIRMED