1. Software Tools for Digital Down-Converters Design
Presented by
Mohsen Shakiba

2. Outline FPGA Tools -MATLAB Tools What’s the Core Generator
DDC Core Description
Design a GSM DDC on a FPGA using DDC Core
-MATLAB Tools
Filter Design Toolbox
Fixed Point Toolbox
Design the GSM DDC filters with Filter Design & Fixed Point Toolboxes

3. Section I
FPGA Tools

4. Benefits of Related FPGA Tools using
More Flexibility
Highly Parametrizable
Real Realtime processing capabilities
Best Option For a SoC Prototype System Design
So Easy for you to Extend and Improve your Design

5. Some of Difficulties More needed Experience
More Time To Target & Market
Poor in integrated Synthesizers and routing tools

6. What’s The Core Generator ?
The CORE Generator™ is a design tool that delivers parameterized IP optimized for Xilinx® FPGAs. It provides a catalog of ready-made functions ranging in complexity from FIFOs and memories to high level system functions such as a
Reed-Soloman Decoder and Encoder,
FIR filters,
FFTs for DSP applications,
standard bus interfaces such as PCI and PCI-X,
and connectivity and networking interfaces (for example, Ethernet, and PCI Express).
It Supports most of Xilinx FPGA Families such as
Spartan™-II
Spartan – 3
Virtex™
Virtex - II
Virtex - II PRO
Virtex - 4

7. Design Flow For a HDL Design
Core-Gen Inserted Here

8. Core Generator Design Environment

9. Digital Down Converter (DDC) Core Features
. Drop-in module for FPGAs
• Configurable data path comprising a mixer, DDS, an optional CIC filter and a series cascade of two (optional) poly phase decimators
• CIC rate changes from 4 to 16383, with support for decimation rate adjustment in real-time
• Two poly phase decimation filters with configurable filter length (0 to 1024 taps) and coefficient precision (1 to 32 bits)
• 0.02 Hz DDS tuning resolution (fclk = 86 MHz, 32bit phase accumulator)
• 25 to 108 dB DDS spurious free dynamic range
• Bias-free convergent rounding employed between datapath components to avoid DC bias issues
• Microprocessor style interface to adjust the CIC decimation rate and tune the DDS

10. Digital Down Converter (DDC) Core Applications
• Software defined radios (SDRs)
• Digital receivers
• Cable modems
• BPSK, QPSK and QAM demodulators
• Spread spectrum communication systems
• CDMA2000 and 3G Basestations

11. Digital Down Converter (DDC) Core Structure
DDC core architecture

12. DDC Core Main Components DDS
DDS unit architecture
Direct digital synthesizers (DDS), or numerically controlled oscillators (NCO), are important components in many digital communication systems. Quadrature synthesizers are used for constructing digital down and up converters, demodulators, and implementing various types of modulation schemes. A common method for digitally generating a complex or real valued sinusoid employs a look-up table scheme. The look-up table stores samples of a sinusoid. A digital integrator is used to generate a suitable phase argument that is mapped by the look-up table to the desired output waveform.

13. DDC Core Main Components DDS
DDS unit architecture
The DDS employed in the DDC uses phase dithering to extend the dynamic range of the heterodyning signal. Dithering also decorrelates the phase angle error , hence minimizing undesirable spectral artifacts (spurs).
sample precision of DDS Output :

14. DDS Spectrum – Single Tone Test samples

15. DDS Spectrum – Frequency sweep Test samples

16. DDS Tuning and Some Design Notations
The DDS can be configured to have a constant output frequency, or it can be programmed using the Core microprocessor style interface.
The output frequency of the DDS waveform is a function of the system sample rate , the number of bits used in the phase accumulator and the phase increment value .
For Example :

17. DDS Tuning and Some Design Notations
The DDS tuning frequency resolution ∆f is a function of the phase accumulator width and the system sample rate
For Example :

18. Digital Down Converter (DDC) Core Structure

19. DDC Core Main Components CIC Decimator
CIC decimation filter
The transfer functions for a single integrator
The transfer function for a single comb stage, referenced to the high input sample rate
The system transfer function for the composite CIC filter, referenced to the high sampling rate

20. DDC Core Main Components CIC Decimator
CIC filter frequency response for N = 4, M = 2, R = 7 and fc =1/8
frequency bands
magnitude frequency response

21. DDC Core Main Components CIC Decimator
CIC filter frequency response for N = 4, M = 1, R = 7 and fc =1/8
frequency bands
magnitude frequency response

22. CIC Decimator Register Growth
The CIC data path experiences internal register growth that is a function of all the design parameters .
The CIC filter uses BMAX bits internally for each of the integrator and differentiator stages, and so produces a full-precision result at the filter output .
Thus Convergent rounding is used to generate the reduced precision sample. If a bit precision greater than BMAX is specified for the CIC output width, this value will be automatically limited to BMAX bits .

23. Digital Down Converter (DDC) Core Structure

24. DDC Core Main Components CFIR & PFIR Filters
CFIR Frequency Response: Typical characteristic.
Poly phase decimator used for both the CFIR and the PFIR

25. DDC Core Pin Descriptions

26. DDC Timing Without any Time Sharing Register write operation.
DDC Core Timings
DDC Timing Without any Time Sharing
Register write operation.

27. DDC Core Parameterization GUI (1)

28. DDC Core Parameterization GUI (2)

29. DDC Core Parameterization GUI (3)

30. DDC Core Parameterization GUI (4)

31. DDC Core Parameterization GUI (5)

32. DDC Core Parameterization GUI (6)

33. DDC Core Parameterization Example For a GSM Application
output sample rate of kHz needed
sample rate change of 192 = 48×2×2 needed

34. DDC Core Parameterization Example For a GSM Application
GSM spectral mask.

35. DDC Core Parameterization Example For a GSM Application
-98,-679,-2016,-3234,-537,850,6053,12060,18230,23239,25212,23239,18230,
12060,6053,850,-2537,-3234,-2016,-679,-98;
coe file content for the polyphase 2:1 decimator G(z) in the GSM DDC design example.
1007,-1853,79,1807,1633,423,265,175,-527,-1331,-1454,-1087, -721, -149, 1008, 1985,2164, 2005, 1483, 61, -1756, -3134, -3953, -4016,-2714, 134,4003, 8361, 12934, 17009, 19565, 20353,19565, 1009, 12934, 8361, 4003, 134,-2714,-4016,
-3953, -3134, -756, 61, 1483, 2005, 2164, 1985,1008, -149, -721, -1087, -1454, -1331, -527, 175,265, 423, 1633, 1807, 79, -1853, 1007;
coe file content for the polyphase 2:1 decimator H(z) in the GSM DDC design example.

36. DDC Core Inserting in a VHDL Code Libraries Declaration
LIBRARY XilinxCoreLib;
USE XilinxCoreLib.c_reg_fd_v7_0_comp.ALL;
USE XilinxCoreLib.c_gate_bit_v7_0_comp.ALL;
USE XilinxCoreLib.c_shift_fd_v7_0_comp.ALL;
USE XilinxCoreLib.c_dist_mem_v7_0_comp.ALL;
USE XilinxCoreLib.c_addsub_v7_0_comp.ALL;
ENTITY gsm_ddc IS
PORT (
CLK : IN STD_LOGIC;
ND : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
RFD : OUT STD_LOGIC;
RDY : OUT STD_LOGIC;
DOUT_I : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
DOUT_Q : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) );
END gsm_ddc;
Libraries Declaration

37. DDC Core Inserting in a VHDL Code
LIBRARY XilinxCoreLib;
USE XilinxCoreLib.c_reg_fd_v7_0_comp.ALL;
USE XilinxCoreLib.c_gate_bit_v7_0_comp.ALL;
USE XilinxCoreLib.c_shift_fd_v7_0_comp.ALL;
USE XilinxCoreLib.c_dist_mem_v7_0_comp.ALL;
USE XilinxCoreLib.c_addsub_v7_0_comp.ALL;
ENTITY gsm_ddc IS
PORT (
CLK : IN STD_LOGIC;
ND : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
RFD : OUT STD_LOGIC;
RDY : OUT STD_LOGIC;
DOUT_I : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
DOUT_Q : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) );
END gsm_ddc;
Component
Instantitution

38. Section II
MATLAB Tools

39. What is The MATLAB Filter Design Toolbox
The Filter Design Toolbox is a collection of tools that provides advanced techniques for designing, simulating, and analyzing digital filters.
Also it provides :
- Advanced FIR filter design methods, including minimum-order, minimum-phase, constrained-ripple, halfband, Nyquist, interpolated FIR, and nonlinear phase
- Advanced IIR design methods, including arbitrary magnitude, group-delay equalizers, constrained-pole radius, peaking, notching, and comb filters
- Multirate filter design, analysis, and implementation, including cascaded integrator-comb (CIC) fixed-point multirate filters
- A powerful Graphical User Interface

40. What is The MATLAB Fixed Point Toolbox
The Fixed-Point Toolbox provides fixed-point data types in MATLAB® and enables algorithm development by providing fixed-point arithmetic.
The Fixed-Point Toolbox provides you with :
- The ability to define fixed-point data types, scaling, and rounding and overflow methods in the MATLAB workspace
- Bit-true real and complex simulation
- Interoperability with Simulink®, Signal Processing Blockset, Embedded MATLAB, and Filter Design Toolbox

41. Filter Design Toolbox used with the Fixed Point Toolbox
the Filter Design Toolbox provides functions that simplify the design of fixed-point filters and the analysis of quantization effects

42. GSM Digital Down-Conveter Some Filters Design Notations
Multirate filter response must be flat over the bandwidth to within the passband ripple, which must be less than 0.1 dB peak to peak. Looking at the GSM out of band rejection mask shown below, we see that the filter must also achieve 18 dB of attenuation at 100 KHz , 50 dB at 300 KHz & 85 dB at 500 KHz.

43. GSM Digital Down-Conveter Sampling Rate reduce scheme

44. FDATool Global Environment
Implementing the Filter Chain of a GSM Digital Down-Converter Through MATLAB Toolboxes
FDATool Global Environment

45. Implementing the Filter Chain of a GSM Digital Down-Converter Through MATLAB Toolboxes
Implementation of CIC filter with specified parameters in multirate creation section

46. Normalize the Magnitude to 0 dB
Implementing the Filter Chain of a GSM Digital Down-Converter Through MATLAB Toolboxes
Normalize the Magnitude to 0 dB

47. Implementing the Filter Chain of a GSM Digital Down-Converter Through MATLAB Toolboxes
CFIR Filter Design
Filter specifications of CFIR Filter
Fs = (52/48)e6 ; % Sampling frequency 52/48 MHZ
N = 20; % 21 taps
Npow = 5; % Sinc power
w = 0.5; % Sinc frequency factor (Differential delay/2)
Apass = e-4; % 0.01 dB
Astop = 0.01; % 40 dB
Aslope = 60; % 60 dB slope over half the Nyquist range
Fpass = 80e3/(Fs/2); % 80 KHz passband-edge frequency
Design filter.
cfir = firceqrip (N,Fpass,[Apass,Astop],'passedge','slope',Aslope, 'invsinc',[w,Npow]);
precision arithmetic is used.
hcfir = mfilt.firdecim(2,cfir);
set(hcfir,...
'Arithmetic', 'fixed',...
'CoeffWordLength', 16,...
'InputWordLength', 20,...
'InputFracLength', -12);

48. Implementing the Filter Chain of a GSM Digital Down-Converter Through MATLAB Toolboxes
PFIR Filter Design
Filter specifications of PFIR Filter
N = 62; % 63 taps
Fs= 52/(48*2)e6 ; % kHz
F = [0 80e3 100e3 Fs/2]/(Fs/2);
A = [ ]; % Amplitude vector indicating a lowpass response
W = [2 1]; % Weight the passband more than the stopband
Filter Design
pfir = firgr (N,F,A,W);
precision arithmetic is used.
hpfir = mfilt.firdecim(2,pfir);
set(hpfir,...
'Arithmetic', 'fixed',...
'CoeffWordLength', 16,...
'InputWordLength', 20,...
'InputFracLength', -12);

49. Meets the GSM Spectral mask
Implementing the Filter Chain of a GSM Digital Down-Converter Through MATLAB Toolboxes
overall filter response by cascading the normalized CIC and the two FIR filters
Meets the GSM Spectral mask

50. References - MATLAB Filter Design & Fixed Point Toolboxes
- DDC & DDS Cores DataSheet ( Xilinx Core generator Documentations)
- FPGA-based applications for software radio – Angsuman Rudra –

51. Thanks for your consideration