1. Augusto Panecatl Technical Information and Customer Support
ARM Cortex M0+®
Augusto Panecatl
Technical Information and Customer Support

2. Cortex-M0 processors
Cortex-M series processors have been specifically developed for the microcontroller industry where the need for fast, highly deterministic, interrupt management is coupled with the desire for extremely low gate count and lowest possible power consumption.
La serie de procesadores Cortex-M se han desarrollado principalmente para el dominio microcontrolador donde la necesidad de rápida altamente determinista, la gestión, la interrupción es, junto con el deseo de recuento extremadamente bajo puerta y el más bajo consumo de energía posible.
Applications include:
Microcontrollers
Mixed signal devices
Smart sensors
Automotive body electronics and airbags

3. Cortex-M0 processors Energy efficiency
Run at lower MHz or during shorter activity periods
Architected support for sleep modes
Smaller code
High density instruction set
Achieve more per byte than 8/16-bit devices

4. Cortex-M0 processors Ease of use
Global standard across multiple vendors
Code compatibility
High Performance

5. Cortex-M0 Processors
Cortex-M family processors are all binary upwards compatible, enabling software reuse and a seamless progression from one Cortex-M processor to another.

6. Cortex M Scalability
Code fully upward compatible with Kinetis K Cortex-M4

7. ARM Cortex-M0+ : The True 8-bit Replacement
The smallest, lowest-power ARM processor on the market
Processor consumption as low as 9μA/MHz*
Outstanding results of 1.77 CoreMark/MHz
I/O low-power improvements with single cycle access to critical peripherals (GPIO …)
Relocatable vector table allows for dynamic exception handlers by moving the vector table into RAM
Micro trace buffer brings fast debug advantages of trace to low-end MCUs

8. Cortex-M0+ 32-bit RISC processor
2-stage pipeline von Neumann architecture
ARMv6-M architecture
16-bit Thumb instruction set with Thumb-2 technology.
Load-Store Architecture
56 Instructions
Because there are several generations of ARM processors, the architectures of these processors are also divided into different version.
Where each version defines a programmers model, instruction set, exception mechanism.

9. Simplified Block Diagram
NVIC The NVIC is an embedded interrupt controller that supports low latency interrupt
processing. Up to 32 Interrupt signals. Priority features, tail-chaining and External NMI.
The system timer SysTick, is a 24-bit count-down timer. Use this as a Real Time
Operating System (RTOS) tick timer or as a simple counter
WIC can detect an interrupt and wake the processor from deep sleep mode.
The WIC is not programmable, and does not have any registers or user interface.
When the WIC is enabled and the processor enters deep sleep mode, the power management unit
in the system can power down most of the Cortex-M0+ processor.
MPU –
Debug System: It allows to handle breakpoint and watchpoints.
Debug Access Port . JTAG or Serial Wire .(5 & 2 lines)

10. Nested Vectored Interrupt Controller (NVIC)
En profundidad: Nested Vectored controlador de interrupciones (CNTV)
El CNTV es una parte integral de todos los procesadores Cortex-M y ofrece excelentes capacidades de manejo de interrupciones de los transformadores. En los procesadores Cortex-M0, Cortex-M0 + y Cortex-M1, el apoyo NVIC hasta 32 interrupciones (IRQ), una interrupción no enmascarable (NMI) y varias excepciones del sistema. Los procesadores Cortex-M3 y Cortex-M4 se extienden del CIV para soportar hasta 240 IRQ, NMI 1 y otras excepciones del sistema.

11. Programmers model
Thread mode Executes application software. The processor enters Thread mode when it
comes out of reset.
Handler mode Handles exceptions. The processor returns to Thread mode when it has
finished all exception processing
Unprivileged The software:
• has limited access to system registers using the MSR and MRS
instructions, and cannot use the CPS instruction to mask interrupts
• cannot access the system timer, NVIC, or system control block
• might have restricted access to memory or peripherals.
Unprivileged software executes at the unprivileged level.
Privileged The software can use all the instructions and has access to all resources.
Privileged software executes at the privileged level.
Stacks
The processor uses a full descending stack.

12. Memory model 4GB of memory address space Code Region SRAM Region
Peripheral Region
RAM Region
Device Region
Internal Private Peripheral Bus
Divided into a number of regions. Each region has its recommended usage.
Support only aligned transfers
External Device .- 2* 512MB does not allow program execution. Used for general data storage.
External RAM MB allows program execution
Peripheral. Not execution allowed. Connected to AHB bus or APB.
SRAM.- 512MB
Code.- Vector Table, code and data.

13. ARM Cortex-M0+ Processor: Low Power by Design
Dedicated features built-in the processor:
WFI & WFE instructions: set core into SLEEP and Wait-For-Event/Interrupt
Sleep-on-Exit: automatic SLEEP after interrupt execution
Few cycles to switch between run and sleep
DEEP SLEEP for longer sleep period:
CPU and NVIC unpowered
WIC monitors wake-up sources
Static processor leakage in nW
KINETIS L implementation:
Asynchronous WIC (AWIC)
Multiple WU sources: periph/LV/NMI
Additionnal LLWU for low leakage wake up
ISR exit
Active Mode
ISR
Sleep Mode
Sleep Mode
SLEEPONEXIT bit set
WFI or WFE

14. Ultra-low Power Modes
Expands beyond typical run, sleep and deep sleep modes with power options designed to maximize battery life in varying applications
Mode
Definition
Run
MCU can be run at full speed. Supports Compute Operation clocking option where bus and system clock are disabled for lowest power core processing and energy-saving peripherals with an alternate asynchronous clock source are operational.
VLP Run
(VLPR)
MCU maximum frequency is restricted to 4MHz core/platform and 1 MHz bus/flash clock. Supports Compute Operation clocking option. LVD protection is off and flash programming is disallowed.
Wait
Allows all peripherals to function, while CPU goes to sleep reducing power consumption. No Compute Operation clocking option.
VLP Wait
(VLPW)
Similar to VLP Run, with CPU in sleep to further reduce power. No Compute Operation clocking option.
Stop
MCU is in static state with LVD protection on. Energy-saving peripherals are operational with Asynchronous DMA (ADMA) feature that can wake-up DMA to perform transfer and return to current mode when complete. AWIC detects wake-up source for CPU. Lowest power mode with option to keep PLL active.
VLP Stop
(VLPS)
MCU is in static state with LVD protection off. Energy-saving peripherals are operational with ADMA feature. AWIC detects wake-up source for CPU.
LL Stop
(LLS)
MCU is in low leakage state retention power mode. LLWU detects wake-up source for CPU including LPTMR, RTC, TSI, CMP, and select pin interrupts. Fast <4.3us wake-up.
VLL Stop 3 (VLLS3)
MCU is placed in a low leakage mode powering down most internal logic. All system RAM contents are retained and I/O states held. LLWU controls wake-up source for CPU similar to LLS mode.
VLL Stop 1
(VLLS1)
Similar to VLLS3 with no RAM or register file retention.
VLL Stop 0
(VLLS0)
Pin wakeup supported. LPTMR, RTC, TSI and CMP wake-up supported with external clock. No RAM or register file retention. Optional POR brown-out detection circuitry.
RUN
SLEEP
DEEP SLEEP

15. Crystal Oscillator (low & high range)
Kinetis L Series: Master Block Diagram
System
Clock Management
Energy Management
Unique ID
ARM Cortex-M0+ Core
Ultra-low power
48MHz bus freq.
Debug
(SWD)
COP
LPO
(1KHz)
Crystal Oscillator (low & high range)
LS Osc
(32KHz)
Voltage Regulator
RST
Flash
8-256K
RAM
1-32K
DMA 4-ch
FLL
PLL
ULP Osc
(4MHz)
Power On Reset
Low Voltage Detector
Peripheral Bus
Analog Interfaces
Timers
Communication
Connectivity
I/O Ports
ADC (SAR w/ DMA)
12/16-bit, up to 16ch
PIT
2ch, 32bit
16b LPTPM
6ch x1, 2ch x 2
UART x2
LPUARTx1
IIS x1
USB FS/LS Transceiver
Up to 80 GPIO
(4 High Dive)
w/ 25 interrupt
SPI x 2
USB Controller
12-bit DAC
HSCMP
SRTC
Temp. Compensated
LPTMR
TSI x 16ch
RST/
Input
I2C x 2
V Regulator
HMI
Operation in:
Run
Wait
Stop/
VLPS
VLLS3
VLLS1
VLLS0
Segment LCD
51x8/55x4
Packages: 16QFN, 20WLCSP, 24QFN, 32LQFP, 32QFN, 35WLCSP, 48LQFP, 48QFN, 64LQFP, 80LQFP, 100LQFP, 121MBGA