1. Co-processors for speeding up drug design algorithms
Advait Jain
Priyanka Jindal
Pulkit Gambhir
Under the guidance of:
Prof. M Balakrishnan
Prof. Kolin Paul

2. Objective
To design FPGA based hardware accelerators for speeding up the energy minimization process.

3. Single Point Precision
minEnergyCG()
Precision lost here
diffEnergy()
evalEnergy_for_step()
Instability introduced here
Resulting in NaN
moveStep()

4. Single Point Precision
Removed the instability
Parabolic interpolation replaced by lnsearch() whenever points are colinear.
Time taken to evaluate the energy increased.
Increase in the number of calls to evalEnergy_for_step().

5. Slow Float Vs Double: Time Plot

6. Slow Float Vs Double: # of evalEnergy_for_step() calls

7. Control Flow

8. Single Point Precision (Molecule Size: 2008 SD:100 CG: 150)
# of Calls to:
EvalEnergyforStep()
Double
642
Slow Float
893
From: minEnergyCG()
450
From: lnSearch()
192
443
Double
Slow Float
# of Calls to:
lnSearch()
100
177
evalEnergyForStep() per lnSearch()
1.92
2.5

9. Reducing the number of Calls
minEnergyCG:
Parabolic interpolation – which 3pts to choose.
Lnsearch :
Iteratively calculates the step size.
When to stop the iteration determined by 2 tolerances.
What we did:
Pts for parabolic interpolation are further apart
Increased the tolerances till the time to minimize the energy was same as double.
Then profiled to check the actual energy.

10. Fast Float Vs Double: Time Plot

11. Fast Float Vs Double: # evalEnergy_for_step() calls

12. Fast Float Vs Double: Energy Plot

13. Fast Float Vs Double: Energy Plot

14. Fast Float Vs Double: Energy Plot

15. Fast Float Vs Double: Energy Plot

16. Conclusion from this exercise
Located the source of instability.
However converting to float increased the time required for the code to run.
Increasing tolerances again made the code fast.
The energy in case of float did not agree well with double computation.

17. ADM-XRC-II board

18. Ongoing Work Familiarizing ourselves with the ADM-XRC-II board.
Trying to understand sample code for writing to ZBT RAMs, exchanging data with the PC.
Overall block diagram and connections – understood.
Timing – need to look at in more depth.

19. Tentative Schedule Software Profiling August
No. of calls
Cache misses
Effect of parameters
Control Flow Analysis August - September
Flow Diagram
Data parallelism
Floating point precision requirement
Exploring H/W Options Early October
Platform Selection
S/W H/W Partitioning
Implementation Mid-October onwards
Analysis