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Alan Mishchenko UC Berkeley, US Robert Brayton UC Berkeley, US

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Presentation on theme: "Alan Mishchenko UC Berkeley, US Robert Brayton UC Berkeley, US"— Presentation transcript:

1 Efficient Solution of Language Equations Using Partitioned Representations
Alan Mishchenko UC Berkeley, US Robert Brayton UC Berkeley, US Roland Jiang UC Berkeley, US Tiziano Villa DIEGM, University of Udine, Italy Nina Yevtushenko Tomsk State University, Tomsk, Russia

2 Overview Problem formulation Example: Traffic light controller
Partitioned representation Solution based on partitioned representation Experimental results Conclusion

3 Problem Formulation Specification S (i,o) Fixed F (i,v,u,o)
FSM i1 i2 o1 o2 Specification S (i,o) Fixed F (i,v,u,o) Unknown X (u,v) Fixed Unknown i o u v Spec Problem: Given S and F, find the Most General Solution (MGS) X of Solution:

4 Combinational and Sequential Flexibility
Network is a DAG Node has single output Node is a logic function Sequential Network is arbitrary Node has many outputs Node is an FSM logic i1 i2 o1 o2 FSM i1 i2 o1 o2 X Y

5 Computing Most General FSM Solution
Input: Prefix-closed specification S(i,o) and fixed part F(i,v,u,o) Output: Most general FSM (prefix-closed progressive) solution X begin 01 X := Complete( S ) 02 X := Determinize( X ) 03 X := Complement( X ) 04 X := Support( X, (i,v,u,o) ) 05 X := Product( Complete(F), X ) 06 X := Support( X, (u,v) ) 07 X := Determinize( X ) 08 X := Complete( X ) 09 X := Complement( X ) 10 X := PrefixClose( X ) 11 X := Progressive( X, u ) 12 return X end

6 Example: Traffic Light Controller Synthesis
General Topology This example Specification Specification S S I O Fixed Traffic Light z F F V U v Unknown Controller X X

7 Traffic Light Controller (Fixed Part)
.model fixed .inputs v z .outputs Acc .mv v 2 wait go .mv z 3 red green yellow .mv CS, NS 3 Fr Fg Fy .latch NS CS .reset CS Fr .table ->Acc 1 .table v z CS ->NS wait red Fr Fr go red Fr Fg wait green Fg Fg go green Fg Fy wait yellow Fy Fy go yellow Fy Fr .end z = {red, green, yellow} v = {wait, go} Specification S Traffic Light z F v Controller X

8 Traffic Light Controller (Specification)
.model spec .inputs z .outputs Acc .mv z 3 red green yellow .mv CS,NS 4 S1 S2 S3 S4 .table ->Acc 1 .latch NS CS .reset CS S1 .table z CS ->NS red S1 S2 red S2 S3 green S3 S4 yellow S4 S1 .end z = {red, green, yellow} v = {wait, go} Specification S Traffic Light z F v Controller X

9 Traffic Light Controller (Synthesis Script)
echo "Synthesis ..." determinize -lci spec.mva spec_dci.mva support v(2),z(3) spec_dci.mva spec_dci_supp.mva support v(2),z(3) fixed.mva fixed_supp.mva product -l fixed_supp.mva spec_dci_supp.mva p.mva support v(2) p.mva p_supp.mva determinize -lci p_supp.mva p_dci.mva progressive -i 0 p_dci.mva x.mva echo "Verification ..." support v(2),z(3) x.mva x_supp.mva product x_supp.mva fixed_supp.mva prod.mva support v(2),z(3) spec.mva spec_supp.mva check prod.mva spec_supp.mva

10 Traffic Light Controller (Solution)
.model solution .inputs v .outputs Acc .mv v 2 wait go .mv CS, NS 4 \ FrS1 FrS2 FgS3 FyS4 .latch NS CS .reset CS FrS1 .table ->Acc 1 .table v CS ->NS wait FrS1 FrS2 go FrS2 FgS3 go FgS3 FyS4 go FyS4 FrS1 .end z = {red, green, yellow} v = {wait, go} Specification S Traffic Light z F v Controller X

11 Partitioned Representation
FSM i1 i2 o1 o2 Fixed part: Latches u v o i ns cs Fixed Unknown i o u v Spec Output functions: oj = Oj(i,v,cs) Transition functions: nsk = NSk(i,v,cs) Communication functions: um= Um(i,v,cs)

12 Computing with Partitioned Representation
Completion Complementation Product computation Changing support Determinization (subset construction)

13 Completion The output relation is O(i,o,cs) = j[oj  Oj(i,cs)]
For each current state cs, the transitions are not defined iff P(i,o) = cs[O(i,o,cs) & (cs)] Using partitioned representation, this computation becomes P(i,o) = cs[j[oj  Oj(i,cs)] & (cs)] This is a partitioned image computation. Any image computation method can be used.

14 Complementation For non-deterministic automata, requires determinization For deterministic automata, make non-accepting states accepting, and vice versa In the case of partitioned representation, the don’t-care state becomes acceptable, other states become non-acceptable

15 Product Computation Combine the partitions of the two components

16 Changing Support (Lifting and Projecting)
Expanding support is trivial Reducing support requires existential quantification In general, cannot be done on the partitioned representation Therefore, postponed until the determinization step

17 Determinization (Subset Construction)
Start with the subset containing only the initial state. For each subset , compute the subsets reachable through (u, v). Define the acceptance relation: Compute the condition of the transition is into non-accepting states: Restrict the transitions to those that are not contained in Q(u, v): Direct the transition under Q(u, v) to DCN. Complete and redirect the remaining transitions to DCA.

18 Experimental Results Name is the ISCAS benchmark name
i/o/cs is the number of input/output/state variables Fcs/Xcs is the partitioning of the state variables States(X) is the number of states in the solution Mono is the runtime of the monolithic computation in seconds Part is the runtime of partitioned computation is in seconds Ratio is improvement due to the proposed method

19 Conclusions Introduced language solving problems
Showed a simple example Discussed partitioned representation Presented experimental results

20 Future Work Developing methods for finding a particular solution contained in the most general solution Developing efficient sequential synthesis methods without state space traversal


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