1. Embedded Architectures: Configurable, Re-configurable, or what?
viewgraph downloading, for a link see:
Grenoble, France
October
Embedded Architectures: Configurable, Re-configurable, or what?
(position statements)
Reiner Hartenstein
University of
Kaiserslautern
Re-configurable !
Pierre Paulin, STMicro (moderator); Henk Corporaal, IMEC; Reiner Hartenstein, University of Kaiserslautern; Oz Levia, Improv Systems; Marco Pavesi, Italtel; Chris Rowen, Tensilica.
Thursday, Oct 10, session 5, p.m.

2. „Re-configurable Hardware“ ??
Terminology has been highly confusing
„Re-configurable Hardware“ ??
this „Hardware“ is not hard !
it‘s Morphware
We need a concise terminology: a consensus is on the way 2

3. Terminology: DPU versus CPU ...
DPA
DPU: data path unit
DPA: DPU array
GA: gate array
rDPU: reconfigurable DPU
rDPA: reconfigurable DPA
rGA: reconfigurable GA
(r)
DPU
DPU
instruction
sequencer
CPU
DPU is no CPU: there is nothing central - like in a DPA 3

4. Digital System Platforms clearly distinguished
program source running on it
machine paradigm
hardware
(not programmable)
none
morphware
fine grain
rGA (FPGA)
configware
coarse grain
rDPU, rDPA
reconfigurable data stream processor
flowware & configware
anti machine
data stream processor (hardwired)
flowware
instruction stream processor
software
von Neumann machine 4

5. flowware defines ....
time
port #
... which data item at which time at which port x | -
input data streams
DPA
time
port # x - |
output data streams
flowware manipulates the data counter(s) ...
... software manipulates the program counter 5

6. Configware / Flowware Compilation
data streams
intermediate
high level source program
wrapper
flowware
scheduler
r. Data
Path
Array
rDPA
configware
mapper
address generator
data sequencer 6

7. most important contributor to nano SoC
we need rDPAs for:
cellular wireless
multimedia
other applications
relative merits:
performance
flexibility
time to market
product longevity
key functionalities:
to cope with
compute requirements
unstable standards
multiple standards 7

8. Processor Performance4G
Processor Performance
Algorithmic Complexity
(Shannon’s Law) 3G
Memory
(Moore’s
Law)
Transistors/chip
10 000
1000
100 10 1 2G 1G
wireless
microprocessor / DSP
processor speed
Normalized
processor speed
Normalized 8

9. Performance vs. Flexibility
rDPAs go far beyond bridging the gap
rDPA
*) R. Hartenstein: ISIS 1997
rDPAs (reconfigurable computing)*
DeMan [T. Claasen et al.: ISSCC 1999]
MOPS / mW
1000
flexibility
throughput
hard-
wired
hardwired
100
FPGA
Reconfigurable logic 10
von
Neumann
instruction set processors
standard microprocessor
DSP 1
0.1
0.01
0.001 2 1
0.5
0.25
0.13
0.1
0,07
µ feature size 9

10. cSoC for wireless communication et al.
incremental dynamic reconfiguration
Xtreme processing unit (XPU) from PACT
rDPA
Layout for UMC mm CMOS 10

11. Time to Market 11 A Fundamental Paradigm Shift in Silicon Application
Revenue
/ month
Time / months 1 10 20
ASIC
Product 30
Update 1
Product
Update 2
reconfigurable
with
download
[Tom Kean] 11

12. END >>> END 12 © 2001, reiner@hartenstein.de
University of Kaiserslautern
>>> END
END 12

13. >>> Appendix
© 2001,
University of Kaiserslautern
>>> Appendix
Appendix
for discussion 13

14. Why a dichotomy of machine paradigms?
vN: unbalanced
vN bottleneck
stolen from Bob Colwell
caches, ...
data stream machine:
bad message: caches do not help
good message: no vN bottleneck
caches not needed
CPU 14

15. Soap Chip* Platform Template
important: coarse grain morphware
Configware
Software
S/W
C/W
microProg
peripherals
RISC,
VLIW
Config.
MCU
ASIP
S/W
Gen. Purp. RISC, VLIW
Scalable SoC interconnect
ASIC
Mem
Processor
Standard I/O blocks
ROM, Flash
eSRAM eDRAM
DSP
C/W
C/W
FPGA
eFPGA
Standard H/W IP
C/W RC
rDPA
*) System on a programmable Chip
© 2002, 15

16. Programming sources von Neumann instruction stream machine
hardwired only
Anti machine
data stream machine
flowware
reconfigurable or hardwired 16

17. Machine paradigms von Neumann data-stream machine Flowware Software
instruction stream machine
Flowware
Software
Configware
embedded memory architecture* 17

18. new business model needed
Cost
year
product life cycle
design cost
new business model needed
the key enabler: morphware 18

19. Glossary approaching consensus 19 digital system platforms:
platform category
source „running“ on platform
machine paradigm
hardware
(not programmable)
none
ISP**
software
von Neumann
morphware
configware
FPGA: none
data stream processor (AMP*)
flowware
anti machine
reconfigurable AMP (rAMP)
flowware & configware
DPU data path unit
rDPU reconfigurable DPU
DPA data path array (DPU array)
rDPA reconfigurable DPA
ISP instruction set processor
AM anti machine
AMP data stream processor*
rAMP reconfigurable AMP
*) no “dataflow machine”
categories of morphware:
morphware use
granularity (path width)
(re)configurable blocks
reconfigurable logic
fine grain (FPGA) (~1 bit)
CLBs
reconfigurable computing
coarse grain (e.g. 32 bits)
rDPUs (e.g. ALU-like)
multi granular: by slice bundling
rDPU slices (e.g. 4 bits)
**) instruction set processor
*) data stream processor 19