1. CSV881: Low-Power Design Power Dissipation in CMOS Circuits
Vishwani D. Agrawal
James J. Danaher Professor
Dept. of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

2. nMOS Logic (Inverters)
For logic 1 input, continuous static power is dissipated.
Saturated-load nMOS
Pseudo-nMOS
R. C. Jaeger and T. N. Blalock, Microelctronic Circuit Design, Third Edition, McGraw-Hill, 2006, Chapter 6.
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Lectures 3, 4: CMOS Circuits

3. Lectures 3, 4: CMOS Circuits
CMOS Logic (Inverter)
VDD
No current flows from power supply!
Where is power consumed?
GND
F. M. Wanlass and C. T. Sah, “Nanowatt Logic using Field-Effect Metal-Oxide-Semiconductor Triodes,” IEEE International Solid-State Circuits Conference Digest, vol. IV, February 1963, pp
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Lectures 3, 4: CMOS Circuits

4. Lectures 3, 4: CMOS Circuits
Components of Power
Dynamic
Signal transitions
Logic activity
Glitches
Short-circuit (small)
Static
Leakage
Ptotal = Pdyn + Pstat
= Ptran + Psc + Pstat
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Lectures 3, 4: CMOS Circuits

5. Power of a Transition: Ptran
V = VDD
R = Ron
i(t)
vi (t)
v(t)
Large
resistance
C = CL
Ground
C = Total load capacitance for gate; includes transistor capacitances
of driving gate + routing capacitance + transistor capacitances
of driven gates; obtained by layout analysis.
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Lectures 3, 4: CMOS Circuits 2

6. Charging of a Capacitor
v(t)
i(t) C V
Charge on capacitor, q(t) = C v(t)
Current, i(t) = dq(t)/dt = C dv(t)/dt
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Lectures 3, 4: CMOS Circuits

7. Lectures 3, 4: CMOS Circuits
i(t) = C dv(t)/dt = [V – v(t)] /R
dv(t) V – v(t)
─── = ─────
dt RC
dv(t) dt
∫ ───── = ∫ ────
V – v(t) RC
– t
ln [V – v(t)] = ── A RC
Initial condition, t = 0, v(t) = 0 → A = ln V
– t
v(t) = V [1 – exp(───)] RC
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

8. Lectures 3, 4: CMOS Circuits
v(t) = V [1 – exp( ── )] RC
dv(t) V – t
i(t) = C ─── = ── exp( ── )
dt R RC
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Lectures 3, 4: CMOS Circuits

9. Total Energy Per Charging Transition from Power Supply
∞ ∞ V2 – t
Etrans = ∫ V i(t) dt = ∫ ── exp( ── ) dt
R RC
= CV2
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Lectures 3, 4: CMOS Circuits

10. Energy Dissipated per Transition in Resistance
∞ V2 ∞ – 2t
R ∫ i2(t) dt = R ── ∫ exp( ── ) dt
R RC 1
= ─ CV2 2
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Lectures 3, 4: CMOS Circuits

11. Energy Stored in Charged Capacitor
∞ ∞ – t V – t
∫ v(t) i(t) dt = ∫ V [1-exp( ── )] ─ exp( ── ) dt
RC R RC 1
= ─ CV2 2
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Lectures 3, 4: CMOS Circuits

12. Lectures 3, 4: CMOS Circuits
Transition Power
Gate output rising transition
Energy dissipated in pMOS transistor = CV2/2
Energy stored in capacitor = CV2/2
Gate output falling transition
Energy dissipated in nMOS transistor = CV2/2
Energy dissipated per transition = CV2/2
Power dissipation:
Ptrans = Etrans α fck = α fck CV2/2
α = activity factor
fck = clock frequency
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

13. Lectures 3, 4: CMOS Circuits
Components of Power
Dynamic
Signal transitions
Logic activity
Glitches
Short-circuit
Static
Leakage
GLITCH
Delay=2 2
Delay =1
1 3
Ptotal = Pdyn + Pstat
= Ptran + Psc + Pstat
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Lectures 3, 4: CMOS Circuits

14. Short Circuit Power of a Transition: Psc
VDD
isc(t)
vi (t)
vo(t) CL
Ground
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Lectures 3, 4: CMOS Circuits 2

15. Short Circuit Current, isc (t)
VDD
VDD - VTp
Vi (t)
n-transistor
cuts-off
Vo(t)
Volt
VTn
p-transistor
starts
conducting
Iscmaxf
isc(t)
Isc
Time (ns) tB tE 1
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Lectures 3, 4: CMOS Circuits

16. Peak Short Circuit Current
Increases with the size (or gain, β) of transistors
Decreases with load capacitance, CL
Largest when CL = 0
Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS ’96, Aug. 1996, pp
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Lectures 3, 4: CMOS Circuits

17. Short-Circuit Energy per Transition
Escf = ∫tBtE VDD isc(t)dt
= (tE – tB) Iscmaxf VDD / 2
Escf = tf (VDD - |VTp| - VTn) Iscmaxf / 2
Escr = tr (VDD - |VTp| - VTn) Iscmaxr / 2
Escf = Escr = 0, when VDD = |VTp| + VTn
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Lectures 3, 4: CMOS Circuits

18. Lectures 3, 4: CMOS Circuits
Short-Circuit Power
Increases with rise and fall times of input.
Decreases for larger output load capacitance; large capacitor takes most of the current.
Small, about 5-10% of dynamic power; momentary shorting of supply and ground during opening and closing of transistor switches.
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

19. Short-Circuit Power Calculation
Assume equal rise and fall times
Model input-output capacitive coupling (Miller capacitance)
Use a spice model for transistors
T. Sakurai and A. Newton, “Alpha-power Law MOSFET model and Its Application to a CMOS Inverter,” IEEE J. Solid State Circuits, vol. 25, April 1990, pp
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

20. Lectures 3, 4: CMOS Circuits
Short Circuit Power
Psc = α fck Esc
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

21. Psc, Rise Time and Capacitance
VDD
VDD
Ron
ic(t)+isc(t)
vi (t)
vo(t)
vo(t) CL tr tf
R = large
vo(t)
─── R↑
Ground
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

22. isc, Rise Time and Capacitance
VDD[1 – exp (─────)]
vo(t) R↓(t) C
Isc(t) = ──── = ───────────────
R↑(t) R↑(t)
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Lectures 3, 4: CMOS Circuits

23. iscmax, Rise Time and Capacitance
Small C
Large C
vo(t)
vo(t)
iscmax 1
────
R↑(t) t tf
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Lectures 3, 4: CMOS Circuits

24. Psc, Rise Times, Capacitance
For given input rise and fall times short circuit power decreases as output capacitance increases.
Short circuit power increases with increase of input rise and fall times.
Short circuit power is reduced if output rise and fall times are longer than the input rise and fall times.
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

25. Summary: Short-Circuit Power
Short-circuit power is consumed by each transition (increases with input transition time).
Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power).
Increasing the output load capacitance reduces short-circuit power.
Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power; completely eliminated when VDD ≤ |Vtp| + Vtn .
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

26. Lectures 3, 4: CMOS Circuits
Components of Power
Dynamic
Signal transitions
Logic activity
Glitches
Short-circuit
Static
Leakage
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

27. Lectures 3, 4: CMOS Circuits
Leakage Power
VDD IG
Ground
Gate R
Source
Drain n+ n+
Isub
IPT ID
IGIDL
Bulk Si (p)
nMOS Transistor
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

28. Leakage Current Components
Subthreshold conduction, Isub
Reverse bias pn junction conduction, ID
Gate induced drain leakage, IGIDL due to tunneling at the gate-drain overlap
Drain source punchthrough, IPT due to short channel and high drain-source voltage
Gate tunneling, IG through thin oxide; may become significant with scaling
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Lectures 3, 4: CMOS Circuits

29. Drain to Source Current
IDS = μ0 Cox (W/L) Vt2 exp{(VGS –VTH ) / nVt }
μ0: carrier surface mobility
Cox: gate oxide capacitance per unit area
L: channel length
W: gate width
Vt = kT/q: thermal voltage
n: a technology parameter
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

30. IDS for Short Channel Device
IDS= μ0 Cox(W/L)Vt2 exp{(VGS –VTH + ηVDS)/nVt}
VDS = drain to source voltage
η: a proportionality factor
W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submicron
Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp
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Lectures 3, 4: CMOS Circuits

31. Subthreshold Current, Isub
Example: 90nm CMOS inverter
L = 90nm, Wp = 495nm, Wn = 216nm
Temperature 300K (room temperature)
Input set to 0 volt
Vthn = 0.291V, Vthp =0.209V at VDD = 1.2V (nominal)
PTM (predictive technology model)
Spice simulation for leakage current
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Lectures 3, 4: CMOS Circuits

32. Subthreshold Current, Isub
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Lectures 3, 4: CMOS Circuits

33. Subthreshold Current, Isub
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Lectures 3, 4: CMOS Circuits

34. Increased Subthreshold Leakage
Scaled device Ic
Log (Drain current)
Isub
VTH’
VTH
Gate voltage
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Lectures 3, 4: CMOS Circuits

35. Summary: Leakage Power
Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power.
For a gate it is a small fraction of the total power; it can be significant for very large circuits.
Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking.
Multiple-threshold devices are used to reduce leakage power.
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

36. Lectures 3, 4: CMOS Circuits
CMOS Gate Power
v(t) V
R = Ron
i(t)
vi (t)
v(t)
i(t)
Large
resistance C
isc(t)
isc(t)
Ground
Leakage
current
time
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Lectures 3, 4: CMOS Circuits 2

37. Lectures 3, 4: CMOS Circuits
Technology Scaling
Scaling down 0.7 micron by factors 2 and 4 leads to 0.35 and 0.17 micron technologies
Constant electric field assumed
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Lectures 3, 4: CMOS Circuits

38. Constant Electric Field Scaling
B. Davari, R. H. Dennard and G. G. Shahidi, “CMOS Scaling for High Performance and Low Power—The Next Ten Years,” Proc. IEEE, April 1995, pp
Other forms of scaling are referred to as constant-voltage and quasi-constant-voltage.
Copyright Agrawal, 2011
Lectures 3, 4: CMOS Circuits

39. Lectures 3, 4: CMOS Circuits
Bulk nMOSFET
Polysilicon
Gate
Drain
Source W n+ n+ L
p-type body (bulk)
SiO2
Thickness = tox
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Lectures 3, 4: CMOS Circuits

40. Lectures 3, 4: CMOS Circuits
Technology Scaling
A scaling factor (S ) reduces device dimensions as 1/S.
Successive generations of technology have used a scaling S = √2, doubling the number of transistors per unit area. This produced 0.25μ, 0.18μ, 0.13μ, 90nm and 65nm technologies, continuing on to 45nm, 32nm and 22nm.
A 5% gate shrink (S = 1.05) is commonly applied to boost speed as the process matures.
N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Boston:
Pearson Addison-Wesley, 2005, Section
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Lectures 3, 4: CMOS Circuits

41. Constant Electric Field Scaling
Device Parameter
Scaling
Length, L
1/S
Width, W
Gate oxide thickness, tox
Supply voltage, VDD
Threshold voltages, Vtn, Vtp
Substrate doping, NA S
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Lectures 3, 4: CMOS Circuits

42. Constant Electric Field Scaling(Cont.)
Device Characteristic
Scaling β
W / (L tox) S
Current, Ids
β (VDD – Vt ) 2
1/S
Resistance, R
VDD / Ids 1
Gate capacitance, C
W L / tox
Gate delay, τ RC
Clock frequency, f
1/ τ
Dynamic power per gate, P
CV 2 f
1/S 2
Chip area, A
Power density
P/A
Current density
Ids /A
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Lectures 3, 4: CMOS Circuits

43. Problem: A Design Example
A battery-operated 65nm digital CMOS device is found to consume equal amounts (P ) of dynamic power and leakage power. The short-circuit power is negligible. The energy consumed by a computing task, that takes T seconds, is 2PT.
Compare two power reduction strategies for extending the battery life:
Clock frequency is reduced to half, keeping all other parameters constant.
Supply voltage is reduced to half. This slows the gates down and forces the clock frequency to be lowered to half of its original (full voltage) value. Assume that leakage current is reduced by a ratio 10/2 = 5 (see slides 32 and 33).
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Lectures 3, 4: CMOS Circuits

44. Solution: Strategy A. Clock Frequency Reduction
Reducing the clock frequency will reduce dynamic power to P / 2, keep the static power the same as P, and double the execution time of the task.
Energy consumption for the task will be,
Energy = (P / 2 + P ) 2T = 3PT
which is greater than the original 2PT.
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Lectures 3, 4: CMOS Circuits

45. Solution: Part B. Supply Voltage Reduction
When the supply voltage and clock frequency are reduced to half their values, dynamic power is reduced to P / 8 and static power to P / 10. The time of task is doubled and the total energy consumption is,
Energy = (P / 8 + P / 10) 2T = 9PT / 20 =0.45PT
The voltage reduction strategy reduces energy consumption while a simple frequency reduction consumes more energy.
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Lectures 3, 4: CMOS Circuits

46. Comparing Strategies A and B
Original A B
Voltage V
V/2
Clock Frequency F
F/2
Task Duration T 2T
Power 2P
1.5P
0.225P
Energy
2PT
3PT
0.45PT
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Lectures 3, 4: CMOS Circuits