1. Lecture 12 Advanced Combinational ATPG Algorithms
FAN – Multiple Backtrace (1983)
TOPS – Dominators (1987)
SOCRATES – Learning (1988)
Legal Assignments (1990)
EST – Search space learning (1991)
BDD Test generation (1991)
Implication Graphs and Transitive Closure ( )
Recursive Learning (1995)
Test Generation Systems
Test Compaction
Summary
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VLSI Test: Lecture 12

2. FAN -- Fujiwara and Shimono(1983) FANout – oreineted test generaton
New concepts:
Immediate assignment of uniquely-determined signals
Unique sensitization
Stop Back trace at head lines
Multiple Back trace
-Rather than stopping at PIs, back tracing in
FAN may stop at internal lines. (head lines)
- Rather than trying to satisfy one objective,
FAN uses a multiple-back trace procedure
that attempts to simultaneously satisfy a set of objectives
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3. PODEM Fails to Determine Unique Signals
Behavior of PODEM
Backtracing operation fails to set all 3 inputs of gate L to 1
Causes unnecessary search
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4. FAN -- Early Determination of Unique Signals
Determine all unique signals implied by current decisions immediately
Avoids unnecessary search
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5. PODEM Makes Unwise Signal Assignments
Blocks fault propagation due to assignment J = 0
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6. Unique Sensitization of FAN with No Search
Path over which fault is uniquely sensitized
FAN immediately sets necessary signals to propagate fault
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7. Headlines HL FL BL
Headlines H and J separate circuit into 3 parts, for which test generation can be done independently
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8. Bound Line: is a line, that is reachable from at least one stem.
Free Line : is a line that is not bound.
Head Line : is a free line that directly feeds a bound line , this line can be justified to logic 0 or 1 from the headline
back to the circuit PIs.
Stem
A, B, C, E, F,G are free lines
Fig.6.32
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9. Contrasting Decision Trees
FAN decision tree
PODEM decision tree
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10. Multiple Backtrace PODEM – Depth-first search 6 times
FAN – breadth-first
passes –
1 time
PODEM –
depth-first
passes – 6 times
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PODEM – Depth-first search
6 times

11. AND Gate Vote Propagation
[5, 3]
[0, 3]
[5, 3]
[0, 3]
[0, 3]
AND Gate
X Easiest-to-control Input –
# 0’s = OUTPUT # 0’s
# 1’s = OUTPUT # 1’s
All other inputs --
# 0’s = 0
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12. Multiple Backtrace Fanout Stem Voting
[5, 1]
P is a stem not reachable
From the fault Site ;
If n0(p)>0 , and n1(p)>0
There is a conflict On P
FAN sets P to 0 if
n0(p)>n1(p) and otherwise
sets P=1
FAN immediately does
a forward implication
from P , and find a signal conflict
much sooner than a single
backtrace procedure.
[1, 1]
[3, 2]
[18, 6]
[4, 1]
[5, 1]
Fanout Stem --
# 0’ s = S Branch # 0’s,
# 1’s = S Branch # 1’s
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13. Multiple Backtrace Algorithm
repeat
remove entry (s, vs) from current_objectives;
If (s is head_objective) add (s, vs) to head_objectives;
else if (s not fanout stem and not PI)
vote on gate s inputs;
if (gate s input I is fanout branch)
vote on stem driving I;
add stem driving I to stem_objectives;
else add I to current_objectives;
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14. Rest of Multiple Backtrace
if (stem_objectives not empty)
(k, n0 (k), n1 (k)) = highest level stem from stem_objectives;
if (n0 (k) > n1 (k)) vk = 0;
else vk = 1;
if ((n0 (k) != 0) && (n1 (k) != 0) && (k not in fault
cone))
return (k, vk);
add (k, vk) to current_objectives;
return (multiple_backtrace (current_objectives));
remove one objective (k, vk) from head_objectives;
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15. Multiple trace generating Conflicting value on a stem
Example for following circuit `execute multiple trace algo. Starting with (I,1) and (J,0) as current objectives. 1
(I, 1)
(J, 0 )
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16. 1
Step 1 1
Current Objectives processed entry stem objectives Head objectives
(I,1), (J,0) (I,1) 1
Step 2
Current Objectives processed entry stem objectives Head objectives
(G,0), (J,0) (J,0)
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17. 1
Step 3 1
Current Objectives processed entry stem objectives Head objectives
(G,0), (H,1) (G,0) 1 1 1
Step 4 1
Current Objectives processed entry stem objectives Head objectives
(H,1), (A1,1) , (E1,1) (H,1)
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18. 1 1 1
Step 5 1 1 1
Current Objectives processed entry stem objectives Head objectives
(A1,1), (E1,1), (E2,1),(C,1) (A1,1) A 1 1 1 1
Step 6 1 1 1
Current Objectives processed entry stem objectives Head objectives
(E1,1), (E2,1) , (C,1) (E1,1) A,E
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19. 1 1 1
Step 7 1 1 1
Current Objectives processed entry stem objectives Head objectives
(E2,1),(C,1) (E2,1) A,E 1 1 1
Step 8 1 1 1
Current Objectives processed entry stem objectives Head objectives
(C,1) (C,1) A,E C
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20. 1 1 1
Step 9 1 1 1
Current Objectives processed entry stem objectives Head objectives
Ø A,E C 1 1 1
Stem objectives 1
Step 10 1 1 1
Current Objectives processed entry stem objectives Head objectives
(E,1) (E,1) A C
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21. 1 1 1
Step 11 1 1 1 1
Current Objectives processed entry stem objectives Head objectives
(A2,0) (A2,0) A C 1 1 1 1 1
Step 12 1
(A, v)
V ε [0,1] 1 1
Current Objectives processed entry stem objectives Head objectives
Ø A C
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22. TOPS – Dominators Kirkland and Mercer (1987)
Tops found even more assignments than FAN
Using Dominators
A Dominator is a circuit signal through witch the
Fault effect has to pass in order to be detected at
A particular PO
An absolute dominator is a dominator through the
Fault effect has to pass to be detected at any PO
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23. l and n are absolute dominator of A
k and n are absolute dominator of B
g,k and n are absolute dominator of C
k and n are absolute dominator of D
m and n are absolute dominator of E
Relative – dominates only paths to a given PO
If dominator of fault becomes 0 or 1, backtrack

24. SOCRATES Learning (1988) Static and dynamic learning:
a = f = 1 means that we learn f = a = 0
by applying the Boolean contrapositive theorem
Set each signal first to 0, and then to 1
Discover implications
Learning criterion: remember f = vf only if:
f = vf requires all inputs of f to be non-controlling
A forward implication contributed to f = vf
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25. Improved Unique Sensitization Procedure
When a is only D-frontier signal, find dominators of a and set their inputs unreachable from a to 1
Find dominators of single D-frontier signal a and make common input signals non-controlling(b=1)
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26. Constructive Dilemma [(a = 0) (i = 0)] [(a = 1) (i = 0)] (i = 0)
If both assignments 0 and 1 to a make i = 0, then i = 0 is implied independently of a
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27. Modus Tollens and Dynamic Dominators
(f = 1) [(a = 0) (f = 0)] (a = 1)
Dynamic dominators:
Compute dominators and dynamically learned implications after each decision step
Too computationally expensive
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28. EST – Dynamic Programming (Giraldi & Bushnell) Equivalent STate hashing
E-frontier – partial circuit functional decomposition
Equivalent to a node in a BDD
Cut-set between circuit part with known labels and part with X signal labels
EST learns E-frontiers during ATPG and stores them in a hash table
Dynamic programming – when new decomposition generated from implications of a variable assignment, looks it up in the hash table
Avoids repeating a search already conducted
Terminates search when decomposition matches:
Earlier one that lead to a test (retrieves stored test)
Earlier one that lead to a backtrack
Accelerated SOCRATES nearly 5.6 times
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29. Fault B sa1 X
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30. Fault h sa1 X
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31. Implication Graph ATPG Chakradhar et al. (1990)
Model logic behavior using implication graphs
Nodes for each literal and its complement
Arc from literal a to literal b means that if a = 1 then b must also be 1
Extended to find implications by using a graph transitive closure algorithm – finds paths of edges
Made much better decisions than earlier ATPG search algorithms
Uses a topological graph sort to determine order of setting circuit variables during ATPG
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32. Example and Implication Graph
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33. Transitive Closure D E
Given a digraph G, the transitive closure of G is the digraph G* such that
G* has the same vertices as G
if G has a directed path from u to v (u  v), G* has a directed edge from u to v
The transitive closure provides reachability information about a digraph B G C A D E B C A G*
Directed Graphs

34. Graph Transitive Closure
When d set to 0, add edge from d to d, which means that if d is 1, there is conflict
Can deduce that (a = a , F=F , b=b) a=b=f=1
When d set to 1, add edge from d to d
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35. Consequence of F = 1 Boolean false function F (inputs d and e) has deF
For F = 1, add edge F F so deF reduces to d e
To cause de = 0 we add edges: e d and d e
Now, we find a path in the graph b b
So b cannot be 0, or there is a conflict
Therefore, b = 1 is a consequence of F = 1
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36. f= A=b =c=1
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37. Related Contributions
Larrabee – NEMESIS -- Test generation using satisfiability and implication graphs
Chakradhar, Bushnell, and Agrawal – NNATPG – ATPG using neural networks & implication graphs
Chakradhar, Agrawal, and Rothweiler – TRAN --Transitive Closure test generation algorithm
Cooper and Bushnell – Switch-level ATPG
Agrawal, Bushnell, and Lin – Redundancy identification using transitive closure
Stephan et al. – TEGUS – satisfiability ATPG
Henftling et al. and Tafertshofer et al. – ANDing node in implication graphs for efficient solution
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38. Recursive Learning Kunz and Pradhan (1992)
Applied SOCRATES type learning recursively
Maximum recursion depth rmax determines what is learned about circuit
Time complexity exponential in rmax
Memory grows linearly with rmax
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39. Recursive_Learning Algorithm
for each unjustified line
for each input: justification
assign controlling value;
make implications and set up new list of unjustified lines;
if (consistent) Recursive_Learning ();
if (for all signals f with same value V for all consistent justifications)
learn f = V;
make implications for all learned values;
if (all justifications inconsistent)
learn current value assignments as consistent;
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40. Recursive Learning i1 = 0 and j = 1 unjustifiable – enter learning a1h h1 a2 b2 e2 f2 c2 g2 i2
j = 1 d2 h2 k
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41. Justify i1 = 0 Choose first of 2 possible assignments g1 = 0 a1 a b b1d d1 h h1 a2 b2 e2 f2 c2 g2 i2
j = 1 d2 h2 k
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42. Implies e1 = 0 and f1 = 0 Given that g1 = 0 a1 a e1 = 0 b b1 c1 c
j = 1 d2 h2 k
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43. Justify a1 = 0, 1st Possibility
Given that g1 = 0, one of two possibilities
a1 = 0 a
e1 = 0 b b1 c1 c
g1 = 0
i1 = 0 d d1
f1 = 0 h h1 a2 b2 e2 f2 c2 g2 i2
j = 1 d2 h2 k
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44. Implies a2 = 0 Given that g1 = 0 and a1 = 0 a1 = 0 a e1 = 0 b b1 c1 c
f1 = 0 h h1
a2 = 0 b2 e2 f2 c2 g2 i2
j = 1 d2 h2 k
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45. Implies e2 = 0 Given that g1 = 0 and a1 = 0 a1 = 0 a e1 = 0 b b1 c1 c
f1 = 0 h h1
a2 = 0
e2 = 0 b2 f2 c2 g2 i2
j = 1 d2 h2 k
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46. Now Try b1 = 0, 2nd Option Given that g1 = 0 a1 a e1 = 0 b b1 = 0 c1 c
f1 = 0 h h1 a2 e2 b2 f2 c2 g2 i2
j = 1 d2 h2 k
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47. Implies b2 = 0 and e2 = 0 Given that g1 = 0 and b1 = 0 a1 a e1 = 0 bc1 c
g1 = 0
i1 = 0 d d1
f1 = 0 h h1 a2
e2 = 0
b2 = 0 f2 c2 g2 i2
j = 1 d2 h2 k
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48. Both Cases Give e2 = 0, So Learn Thatd d1
f1 = 0 h h1 a2
e2 = 0 b2 f2 c2 g2 i2
j = 1 d2 h2 k
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49. Justify f1 = 0 Try c1 = 0, one of two possible assignments a1 a e1 = 0d d1
f1 = 0 h h1 a2
e2 = 0 b2 f2 c2 g2 i2
j = 1 d2 h2 k
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50. Implies c2 = 0 Given that c1 = 0, one of two possibilities a1 a e1 = 0d d1
f1 = 0 h h1 a2
e2 = 0 b2
c2 = 0 f2 g2 i2
j = 1 d2 h2 k
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51. Implies f2 = 0 Given that c1 = 0 and g1 = 0 a1 a e1 = 0 b b1 c1 = 0 c
j = 1 d2
f2 = 0 h2 k
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52. Try d1 = 0 Try d1 = 0, second of two possibilities a1 a e1 = 0 b b1 c1
g1 = 0
i1 = 0 d
d1 = 0
f1 = 0 h h1 a2
e2 = 0 b2 f2 c2 g2 i2
j = 1 d2 h2 k
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53. Implies d2 = 0 Given that d1 = 0 and g1 = 0 a1 a e1 = 0 b b1 c1 c
f1 = 0 h h1 a2
e2 = 0 b2 f2 c2 g2 i2
j = 1
d2 = 0 h2 k
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54. Implies f2 = 0 Given that d1 = 0 and g1 = 0 a1 a e1 = 0 b b1 c1 c
j = 1
d2 = 0
f2 = 0 h2 k
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55. Since f2 = 0 In Either Case, Learn f2 = 0b b1 c1 c
g1 = 0
i1 = 0 d d1 f1 h h1 a2
e2 = 0 b2 c2 g2 i2
j = 1 d2
f2 = 0 h2 k
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56. Implies g2 = 0 a1 a e1 b b1 c1 c g1 = 0 i1 = 0 d d1 f1 h h1 a2 e2 = 0
j = 1 d2
f2 = 0 h2 k
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57. Implies i2 = 0 and k = 1 a1 a e1 b b1 c1 c g1 = 0 i1 = 0 d d1 f1 h h1
j = 1 d2
f2 = 0 h2
k = 1
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58. Justify h1 = 0 Second of two possibilities to make i1 = 0 a1 a b b1 e1g1
i1 = 0 d d1 h
h1 = 0 a2 b2 e2 f2 c2 g2 i2
j = 1 d2 h2 k
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59. Implies h2 = 0 Given that h1 = 0 a1 a b b1 e1 c1 f1 c g1 i1 = 0 d d1 h
j = 1 d2
h2 = 0 k
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60. Implies i2 = 0 and k = 1 Given 2nd of 2 possible assignments h1 = 0 a1c1 f1 c g1
i1 = 0 d d1 h
h1 = 0 a2 b2 e2 f2 c2 g2
i2 = 0
j = 1 d2
h2 = 0
k = 1
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61. Both Cases Cause k = 1 (Given j = 1), i2 = 0
Therefore, learn both independently a1 a b b1 e1 c1 f1 c g1
i1 = 0 d d1 h h1 a2 b2 e2 f2 c2 g2
i2 = 0
j = 1 d2 h2
k = 1
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62. Other ATPG Algorithms Legal assignment ATPG (Rajski and Cox)
Maintains power-set of possible assignments on each node {0, 1, D, D, X}
BDD-based algorithms
Catapult (Gaede, Mercer, Butler, Ross)
Tsunami (Stanion and Bhattacharya) – maintains BDD fragment along fault propagation path and incrementally extends it
Unable to do highly reconverging circuits (parallel multipliers) because BDD essentially becomes infinite
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63. Fault Coverage and Efficiency
# of detected faults
Total # faults
Fault coverage =
Fault
efficiency
# of detected faults
Total # faults -- # undetectable faults =
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64. Test Generation Systems
Circuit
Description
Fault
List
Compacter
SOCRATES
With fault
simulator
Aborted
Faults
Test
Patterns
Backtrack
Distribution
Undetected
Faults
Redundant
Faults
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65. Test Compaction
Fault simulate test patterns in reverse order of generation
ATPG patterns go first
Randomly-generated patterns go last (because they may have less coverage)
When coverage reaches 100%, drop remaining patterns (which are the useless random ones)
Significantly shortens test sequence – economic cost reduction
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66. Static and Dynamic Compaction of Sequences
Static compaction
ATPG should leave unassigned inputs as X
Two patterns compatible – if no conflicting values for any PI
Combine two tests ta and tb into one test tab = ta tb using D-intersection
Detects union of faults detected by ta & tb
Dynamic compaction
Process every partially-done ATPG vector immediately
Assign 0 or 1 to PIs to test additional faults
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67. Compaction Example t1 = 0 1 X t2 = 0 X 1 t3 = 0 X 0 t4 = X 0 1
Combine t1 and t3, then t2 and t4
Obtain:
t13 = t24 = 0 0 1
Test Length shortened from 4 to 2
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68. Summary Test Bridging, Stuck-at, Delay, & Transistor Faults
Must handle non-Boolean tri-state devices, buses, & bidirectional devices (pass transistors)
Hierarchical ATPG -- 9 Times speedup (Min)
Handles adders, comparators, MUXes
Compute propagation D-cubes
Propagate and justify fault effects with these
Use internal logic description for internal faults
Results of 40 years research – mature – methods:
Path sensitization
Simulation-based
Boolean satisfiability and neural networks
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69. Problems
7.2 , 7.3, 7.5 , 7.7, 7.10,7.12, 7.21, 7,22
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