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XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,

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Presentation on theme: "XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May 2010 Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,"— Presentation transcript:

1 XFEL 2D Pixel Clock and Control System Train Builder Meeting, UCL 11 May Erdem Motuk, Martin Postranecky, Matt Warren, Matthew Wing,

2 A-C Coupling & Latching Test Circuit -1-
-ve LVDS TEST OUTPUT LVDS output 4k7 SK26 100pF SK25 U35 7 U44 12 U11 100R 100R 100R 2k2 CLK IN SK16 100pF SK15 DS90LV110 4k7 DS90LV001 DS90LV110 +ve LVDS TEST OUTPUT 11 May 2010 C+C

3 100 MHz clock 100MHz clock 1= IN+ 2= IN- 3= OUT+ latched
11 May 2010 C+C

4 Paused Signal LONG PAUSE 3= OUT+ latched 4= OUT-latched 11 May 2010
C+C

5 Starting Signal STARTINGSIGNAL 3= OUT+ latched 4= OUT- latched
11 May 2010 C+C

6 Pseudo-Random Signal PSEUDO-RANDOM 1= TTL IN 2= OUT+ latched
11 May 2010 C+C

7 Pseudo-Random Signal - Start
PSEUDO-RANDOM START 1= LVTTL IN 2= OUT+ latched 3= OUT- latched 11 May 2010 C+C

8 AUXILIARY OUTPUT DRIVERS
A-C Coupling & Latching Test Circuit -2- +3v3 1k 1k 4k7 EN U1 EN U2 100pF 5m CAT5 cable 2 1 100R 100R 100R 2k2 100pF 4k7 DS90LV001 DS90LV001 -ve LVDS TEST OUTPUT 3x DS90LV001 AUXILIARY OUTPUT DRIVERS U4 6 U3 Pin5 1 +ve LVDS TEST OUTPUT +3v3 100n RJ45 DS90LV028 DS90LV001 11 May 2010 C+C

9 National DS90LV001 800 Mbps LVDS Buffer Diff. Delay = 1.4ns typ.
Part-to-Part Skew = 0ps typ. / 60ps max. ( for same Vcc & temp. ) Fall / Rise Time = 310ps typ. Peak-to-Peak Data Jitter = 100ps typ. 11 May 2010 C+C

10 Current Tests Differential LVDS Pseudo-random signal from FPGA Development Board ( using 100 MHz clock ) 5 m of CAT5-type cable with RJ45 A-C coupling & latching test circuit -2- Differential LVDS Test Output fed back to FPGA Development Board Compare and log errors for good statistics 11 May 2010 C+C

11 Future Plans Finish testing AC-Coupling & Latching Test Circuit -2-
Yes / No decision on balanced signals ( Manchester coding ? ) ~3 weeks Final FPGA selection ( PLL, Delays ) Finalise Circuit Design of C&C prototype board FPGA Firmware development June - August 2010 Prototype board selection ( DESY ? / RAL ? ) Schematic entry & layout ( RAL ) September – October 2010 C&C Prototype Mk.1 manufacture November 2010 C&C Prototype Mk.1 Testing December 2010 – January 2011 11 May 2010 C+C

12 Single Integrated Prototype Card
Fanout 8 To FEE FPGA TR / Machine etc. Signals or inputs from C&C Master Outputs to Fanouts Master TCP/ IP Local AMC Control PLL etc 11 May 2010 C+C

13 End….. 11 May 2010 C+C

14 Overview C+C Master Bunch Veto FEE C+C Fanout Slave Timing Receiver
μTCA Crate FEE C+C Master MHz Clock C+C Fanout Slave FEE 4 FEE C+C Fanout FEE Crate Processor Start/Info/Stop C+C Fanout Bunch Veto C+C Fanout FEE Status 4 Trigger + Telegram ID MHz Clk 1-20MHz? Clock Trig/Data MINIMUM FANOUT REQUIREMENTS : 16 + Fanouts, expandable 3x Outputs ( diff. LVDS, STP/UTP ) 1x Input ( single line, level only ) Timing Receiver Timing Interface XFEL Other 11 May 2010 C+C

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