1. Final Testbench: tb_final_shp.sv
Message size = 505 bytes → 9 blocks
MD5 = 64 rounds/block
SHA1 = 80 rounds/block
SHA256 = 64 rounds/block
#cycles for 1 round/cycle = 9 * ( ) = 1872
Most implementations require around 2000 cycles (extra cycles needed for overhead)
Not possible to take less than 1872 cycles without unfolding (i.e., doing more than 1 round per cycle)

2. Last Quarter: Top Delay Results
Design 1:
#ALUTs = 6123, #Registers = 1335, Area = 7458
Fmax = MHz, #Cycles = 1772
Delay = microsec, Area*Delay = millisec*area
Design 2:
#ALUTs = 3926, #Registers = 1863, Area = 5789
Fmax = MHz, #Cycles = 1380
Delay = microsec, Area*Delay = millisec*area
Design 3:
#ALUTs = 2150, #Registers = 1172, Area = 3322
Fmax = MHz, #Cycles = 1934
Delay = microsec, Area*Delay = millisec*area

3. Last Quarter: Top Area/Delay Results
Design 1:
#ALUTs = 2150, #Registers = 1172, Area = 3322
Fmax = MHz, #Cycles = 1934
Delay = microsec, Area*Delay = millisec*area
Design 2:
#ALUTs = 2132, #Registers = 1165, Area = 3297
Fmax = MHz, #Cycles = 2003
Delay = microsec, Area*Delay = millisec*area
Design 3:
#ALUTs = 2582, #Registers = 1271, Area = 3853
Fmax = MHz, #Cycles = 1971
Delay = microsec, Area*Delay = millisec*area

4. Last Quarter: Median Results
Median Delay = microsec
Median Area*Delay = millisec*area

5. This Quarter: Minimum Passing
Delay ≤ 50 microsec
Area*Delay ≤ 300 millisec*area

6. Quartus Optimization Modes
You can use different optimization modes for “Delay” results and “Area*Delay” Results (see menu under Compiler Settings)
However, “Performance” mode sometimes lead to worse performance and “Area” mode sometimes lead to worse area.