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Compiler Construction
CS 606 Sohail Aslam Lecture 3 compiler: intro
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Syntax Tree x+2-y goal expr term op – <id,y> <id,x> +
<number, 2> x+2-y
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Abstract Syntax Trees The parse tree contains a lot of unneeded information. Compilers often use an abstract syntax tree (AST).
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Abstract Syntax Trees This is much more concise – + <id,y>
<id,x> <number,2> This is much more concise
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Abstract Syntax Trees – + <id,y> <id,x> <number,2> AST summarizes grammatical structure without the details of derivation
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Abstract Syntax Trees – + <id,y> <id,x> <number,2> ASTs are one kind of intermediate representation (IR)
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The Back End Instruction selection IR machine code errors Register
allocation scheduling
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The Back End Translate IR into target machine code.
Choose machine (assembly) instructions to implement each IR operation
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The Back End Ensure conformance with system interfaces
Decide which values to keep in registers
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The Back End Instruction Selection: Produce fast, compact code.
IR machine code errors Register allocation scheduling Instruction Selection: Produce fast, compact code.
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The Back End Instruction Selection:
IR machine code errors Register allocation scheduling Instruction Selection: Take advantage of target features such as addressing modes.
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The Back End Instruction Selection:
IR machine code errors Register allocation scheduling Instruction Selection: Usually viewed as a pattern matching problem – dynamic programming.
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The Back End Instruction Selection:
IR machine code errors Register allocation scheduling Instruction Selection: Spurred by PDP-11 to VAX CISC.
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The Back End Instruction Selection:
IR machine code errors Register allocation scheduling Instruction Selection: RISC architecture simplified this problem.
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The Back End Register Allocation:
IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Register Allocation: Have each value in a register when it is used.
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The Back End Register Allocation:
IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Register Allocation: Manage a limited set of resources – register file.
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The Back End Register Allocation:
IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Register Allocation: Can change instruction choices and insert LOADs and STOREs.
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The Back End Register Allocation:
IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Register Allocation: Optimal register allocation is NP-Complete.
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The Back End Instruction Scheduling:
IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Instruction Scheduling: Avoid hardware stalls and interlocks.
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The Back End Instruction Scheduling:
IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Instruction Scheduling: Use all functional units productively.
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The Back End Instruction Scheduling:
IR Instruction selection IR Register allocation IR Instruction scheduling machine code errors Instruction Scheduling: Optimal scheduling is NP-Complete in nearly all cases.
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