Presentation is loading. Please wait.

Presentation is loading. Please wait.

CSE378 Midterm Review Moore’s Law -- What are the two versions?

Published byἸαρέδ Τρικούπης Modified over 6 years ago

Similar presentations

Presentation on theme: "CSE378 Midterm Review Moore’s Law -- What are the two versions?"— Presentation transcript:

1 CSE378 Midterm Review Moore’s Law -- What are the two versions?
Is Moore’s Law a law? Explain what an instruction set architecture is [ISA] What do the terms RISC and CISC mean? 12/9/2018 CSE378 Review

2 MIPS ISA Give the uses of the fields of an R-type instruction:
[31-26], [25-21], [20-16], [15-11], [10-6], [5-0] Give the numbers of two registers whose use is specified in the ISA Give the numbers of two registers whose use is agreed-on by programming language convention Give the numbers of two registers whose use is agreed-on by programming convention Explain big-endian and little-endian memory layout 12/9/2018 CSE378 Review

3 More MIPS Explain the difference between instructions performing “signed” and “unsigned” arithmetic Explain the operation of the MIPS memory operations: Load and Store What is a “pseudo-op” or “pseudo instruction”? How is it that the add and subtract instructions can have the same opcode? Explain how to load a full word constant into register $4 12/9/2018 CSE378 Review

4 ALU Bit-slice Give the control signals for NOR What value does
“Less” get assigned? Write a poem about the beauty of 2s- complement math 12/9/2018 CSE378 Review

5 Load Word Give the control line settings for LW 12/9/2018
CSE378 Review

6 Decoding SW Explain what changes if SW’s opcode were , and the “don’t cares” were to be 1 Signal R-type lw sw beq Op Op Op Op Op Op RegDest X X ALUSrc MemtoReg X X RegWrite MemRead MemWrite Branch ALUOp ALUOp OR AND Op5 Op4 Op3 Op2 Op1 Op0 RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOp0 12/9/2018 CSE378 Review

7 Multicycle MIPS Explain purpose of MDR Give control for 2nd cycle
12/9/2018 CSE378 Review

Download ppt "CSE378 Midterm Review Moore’s Law -- What are the two versions?"

Similar presentations

Pipeline Exceptions & ControlCSCE430/830 Pipelining in MIPS MIPS architecture was designed to be pipelined –Simple instruction format (makes IF, ID easy)

Pipeline Exceptions & ControlCSCE430/830 Pipelining in MIPS MIPS architecture was designed to be pipelined –Simple instruction format (makes IF, ID easy)
Pipeline Example: cycle 1 lw R10,9(R1) sub R11,R2, R3 and R12,R4, R5 or R13,R6, R7.

Pipeline Example: cycle 1 lw R10,9(R1) sub R11,R2, R3 and R12,R4, R5 or R13,R6, R7.
The Processor: Datapath & Control

The Processor: Datapath & Control
331 W9.1Spring 2006 14:332:331 Computer Architecture and Assembly Language Spring 2006 Week 9 Building a Single-Cycle Datapath [Adapted from Dave Patterson’s.

331 W9.1Spring :332:331 Computer Architecture and Assembly Language Spring 2006 Week 9 Building a Single-Cycle Datapath [Adapted from Dave Patterson’s.
Levels in Processor Design

Levels in Processor Design
CMPUT 329 - Computer Organization and Architecture II1 CMPUT229 - Fall 2003 TopicE: Building a Data Path and a Control Path for a Microprocessor José Nelson.

CMPUT Computer Organization and Architecture II1 CMPUT229 - Fall 2003 TopicE: Building a Data Path and a Control Path for a Microprocessor José Nelson.
331 Lec 14.1Fall 2002 Review: Abstract Implementation View  Split memory (Harvard) model - single cycle operation  Simplified to contain only the instructions:

331 Lec 14.1Fall 2002 Review: Abstract Implementation View  Split memory (Harvard) model - single cycle operation  Simplified to contain only the instructions:
Preparation for Midterm Binary Data Storage (integer, char, float pt) and Operations, Logic, Flip Flops, Switch Debouncing, Timing, Synchronous / Asynchronous.

Preparation for Midterm Binary Data Storage (integer, char, float pt) and Operations, Logic, Flip Flops, Switch Debouncing, Timing, Synchronous / Asynchronous.
Computer Structure - Datapath and Control Goal: Design a Datapath  We will design the datapath of a processor that includes a subset of the MIPS instruction.

Computer Structure - Datapath and Control Goal: Design a Datapath  We will design the datapath of a processor that includes a subset of the MIPS instruction.
CMPUT 329 - Computer Organization and Architecture II1 CMPUT329 - Fall 2003 TopicH: Building a Data Path and a Control Path for a Microprocessor José Nelson.

CMPUT Computer Organization and Architecture II1 CMPUT329 - Fall 2003 TopicH: Building a Data Path and a Control Path for a Microprocessor José Nelson.
CS 61C discussion 11 (1) Jaein Jeong 2002 Draw the data path: ADD or SUB Clk 555 RwRaRb 32 32-bit Registers Extender Clk WrEn Adr Data Memory ALU Instruction.

CS 61C discussion 11 (1) Jaein Jeong 2002 Draw the data path: ADD or SUB Clk 555 RwRaRb bit Registers Extender Clk WrEn Adr Data Memory ALU Instruction.
Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures1 Machine instructions execution steps (1) FETCH = Read the instruction.

Copyright 1998 Morgan Kaufmann Publishers, Inc. All rights reserved. Digital Architectures1 Machine instructions execution steps (1) FETCH = Read the instruction.
The Datapath Andreas Klappenecker CPSC321 Computer Architecture.

The Datapath Andreas Klappenecker CPSC321 Computer Architecture.
The Multicycle Processor CPSC 321 Andreas Klappenecker.

The Multicycle Processor CPSC 321 Andreas Klappenecker.
Dr. Iyad F. Jafar Basic MIPS Architecture: Multi-Cycle Datapath and Control.

Dr. Iyad F. Jafar Basic MIPS Architecture: Multi-Cycle Datapath and Control.
Supplementary notes for pipelining LW ____,____ SUB ____,____,____ BEQ ____,____,____ ; assume that, condition for branch is not satisfied OR ____,____,____.

Supplementary notes for pipelining LW ____,____ SUB ____,____,____ BEQ ____,____,____ ; assume that, condition for branch is not satisfied OR ____,____,____.
COSC 3430 L08 Basic MIPS Architecture.1 COSC 3430 Computer Architecture Lecture 08 Processors Single cycle Datapath PH 3: Sections 5.1-5.4.

COSC 3430 L08 Basic MIPS Architecture.1 COSC 3430 Computer Architecture Lecture 08 Processors Single cycle Datapath PH 3: Sections
Computer Architecture and Design – ECEN 350 Part 6 [Some slides adapted from A. Sprintson, M. Irwin, D. Paterson and others]

Computer Architecture and Design – ECEN 350 Part 6 [Some slides adapted from A. Sprintson, M. Irwin, D. Paterson and others]
1 A single-cycle MIPS processor  An instruction set architecture is an interface that defines the hardware operations which are available to software.

1 A single-cycle MIPS processor  An instruction set architecture is an interface that defines the hardware operations which are available to software.
CSE331 W10.1Irwin&Li Fall 2006 PSU CSE 331 Computer Organization and Design Fall 2006 Week 10 Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)www.cse.psu.edu/~mji.

CSE331 W10.1Irwin&Li Fall 2006 PSU CSE 331 Computer Organization and Design Fall 2006 Week 10 Section 1: Mary Jane Irwin (

Similar presentations

Ads by Google