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Embedded Computer Architecture 5SIA0 Overview
Henk Corporaal TUEindhoven
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ECA summary The miniMIPS processor some of you built
What you’ll understand after taking 5SIA0 Also, the technology behind chip-scale multiprocessors Photo is of an Intel Conroe (Core 2 Duo Desktop processor). Photo taken from Intel web site. ECA H.Corporaal
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Course goals Learn advanced computer architecture concepts like:
ILP, DLP, and Multi-issue architectures O-O-O execution Correlating branch prediction; Advanced memory hierarchy; speedup methods Energy consumption and Technology issues; etc. Learn multi-processor architecture concepts like: Multi-threading Topologies Synchronization Cache Coherence and Memory Consistency ECA H.Corporaal
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Book Introduction Impact of technology Processor microarchitecture
Memory hierarchies Multiprocessor systems Interconnection networks Coherence, synchronization, and memory consistency Chip multiprocessors Quantitative evaluations We’ll add ‘embedded’, e.g. ARM ECA H.Corporaal
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Organization Credits: Weekly class meetings
5SIA0: 5 credit points (ECTS) Weekly class meetings Tuesdays: (Aud 7) Thursdays: – (Aud 7) Very advanced Labs: largely in your own time Student literature research of TOP recent conferences last week Examination in end of January/early February 2017 ECA H.Corporaal
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Practical Experience 3 lab assignments: Lab assistents:
Design and evaluation of a CGRA (Coarse Grain Reconfigurable Array) processor Extreme parallel (GPU - SIMD) programming Evaluation of a Multi-Core processor Lab assistents: Mark Wijtvliet Luc Waeijen Roel Jordans Mohammad Tahghighi ECA H.Corporaal
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Lab 1: CGRA Co-optimization of application and architecture for a coarse grained reconfigurable architecture ECA H.Corporaal
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Architecture and application
CGRA: Application: Gaussian blur
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Your job: Modify the architecture to: Modify the algorithm Enjoy!
Reduce energy Reduce area Improve performance Modify the algorithm Code optimizations Modify code to use architecture configuration Enjoy!
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Lab 2: GPU - SIMD NVIDIA's PASCAL architecture
One SM: streaming multiprocessor supports FP16, 32 & 64 ECA H.Corporaal
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NVIDIA's PASCAL (5-20 Tflop)
ECA H.Corporaal
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GPU trends (NVIDIA) see: ECA H.Corporaal
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Lab 3: Multicore Assignment!
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What are the objectives?
To get familiar with multiprocessor architectures and their programming models To look at different configurations, e.g., the number of processors, block-size and associativity of different levels of caches. Finally to optimize the Energy-Delay-Area-Product (EDAP) of the system
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What you will learn How to use the GEM5 as cycle accurate simulator to run applications The impacts of different architectural parameters on performance The size of different levels of caches Cache Associativity Applying loop transformation techniques to optimize the memory accesses Applying the application partitioning technique for task level parallelism Using McPAT for power and area estimation
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Schedule 2016-2017 (preliminary)
Date Topic Material Assignments + Remarks 15 Nov Introduction Ch 1 17 Nov Technology Impact Ch 2 22 Nov CGRA and Accelerators: Mark Wijtvliet CGRA assignment (deadline: Dec 8) 24 Nov Processor Architectures - 1 Ch 3 29 Nov Processor Architectures - 2 1 Dec GPU: Zhenyu Ye / Gert-Jan GPU lab (deadline: Jan 9) 6 Dec Processor Architectures - 3 Ch 3; ARM 8 Dec Processor Architectures - 4 13 Dec Memory hierarchy Ch 4 15 Dec Loop transformation for Data Reuse (extended in compiler course) 20 Dec Multiprocessor systems Ch 5 22 Dec GEM5+ Simulation: Mohammad Tahghighi + Luc Waeijen Ch 9 GEM5 multiproc. assign. (deadline: Jan 22) 10 Jan Interconnection networks Ch 6 12 Jan Coherence, synchr. and consistency Ch 7 17 Jan Deep Learing Neural Networks: Maurice Peemen ECA H.Corporaal
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Extra Material Handouts and slides; see course web site: Study recent articles from top conferences and journals Alternative reading book: Computer Architecture A quantitative approach 5th ed. by Hennessy and Patterson ch 1-5, app A-C ECA H.Corporaal
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Where is computing going?
ECA H.Corporaal 18
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