1. COMP 1321 Digital Infrastructure
Richard Henson
University of Worcester
October 2017

2. Week 3: Programming a CPU – The Fetch-Execute Cycle
Explain the instruction set of a typical CPU
Understand the sequential way a CPU uses its instruction set to run programs
Understand how registers and memory addresses are used to process a CPU instruction and store the results

3. Minimalist CPU What is needed to build a successful CPU?
ALU (Arithmetic Logic Unit)
Memory (to store intermediate data))
“Execution Unit”
Input & Output
A Good Name!
Intel’s first (1972) was called…
“4004”… because it had a 4-bit bus!

4. Arithmetic Logic Unit (ALU)
(or… more sophisticated… Integer Execution Unit)
Input A
Input B
Output 5 3 2
add 1 3 2
sub
How could these numbers be represented as data that passes into the ALU?

5. Programming Commands and Machine Code
A set of instructions for the CPU can be put into a program that can be executed one after the other
these instructions are known as machine code
Each type of CPU has its own type of “machine language”.

6. Move data in and out of data memory store
Processing Idea Nr. 1
Move data in and out of data memory store 1.
Move data from memory 5 3 2
add 1 4
Memory DRAM, Hard Disk .. 2. 3.
Move data into memory

7. Sequence of CPU commands
If the CPU is going to do something useful, it needs a sequence of commands
e.g.
move number into ALU from memory
move another number in from memory
add them together
move the result into memory…

8. Move instructions into CPU from code memory
Processing Idea Nr.2
Move instructions into CPU from code memory
Instruction Memory 5 3 2
add 1 4
(Code Memory)
mov 3 in from memory
mov 2 in from memory
add the two numbers
mov the result to memory IP
Program

9. Registers Registers are high-speed memory stores on the CPU chip
Parking places for data on the move 1 4 6 8 AX BX
AX and BX are used for ALU operations
MAR
MAR is memory address register, here 4. So result, 6+8=14 will go into memory cell address 4

10. The computer so far … ip
Data Memory
Instruction
Memory 1 4
mar

11. A couple of extra bits.. Line of code goes in…
Memory Data Register
Instruction Register
Data Memory 1 4 1. 2
add ax,bx 2. 8 34
Instruction
Memory
Data
Energize ax
Energize bx
Select ALU “add" 2
Address 34
Line of code goes in…
Electrical bit signals come out

12. Moving data into Registers
For example …
mov ax , [1]
Instruction
Memory 1 2
mar 3 4 AX
mov ax , [1] BX
mov bx , [2] 5
mov bx , [2] 8 7 8 7 6 1

13. Moving data into Memory
For example …
mov [3] , ax
Instruction
Memory 1 2
mar 3 4
mov [0], bx AX
mov [3] , ax BX 5 7
mov [0] , bx 8 7 8 7 6 8 1

14. … this means ‘ add ax to bx, put the answer in ax’
Adding Numbers
For example …
add ax , bx
Instruction
Memory 1 2
mar 3 4
… this means ‘ add ax to bx, put the answer in ax’ AX
Add ax,bx BX 5 8 7 8 7 8 7 15 6 1

15. Now let’s slow things down…
Today’s CPUs process billions of instructions every second
in the early days (Intel 4004) it was merely millions!
Many great simulators have been produced that can work through a machine code program one cycle, or one instruction, at a time…

16. What is “Processing”? Mostly… calculations by the ALU:
need data input
from register
from external memory
need to store output
Could also be just a command, no data needed…

17. CPU types Most frequently used: We’ll focus on Intel 8086 family
Motorola (esp family)
ARM (many mobile phones)
We’ll focus on Intel 8086 family
dates back to original IBM PC…

18. Role of “Registers” Memory stores inside the CPU
just the right size “word” of data for ALU
typically 1, 2, 4 bytes i.e. very small!
Advantage: CPU reads/writes the data very very quickly to/from the registers

19. Architecture and Buses
Design of CPU
internal connections
external connections to motherboard
data bus (same word as registers)
address bus (depends on no of memory locations)
control bus (messages to/from components)
layout of components on motherboard

20. Registers (summary…) high-speed memory on the CPU chip
Parking places for data on the move 1 4 6 8 AX BX
AX and BX registers are used for ALU operations
MARR
MAR is memory address register, 4 in eg.
Result of processing, 6+8=14, will go into memory address 4

21. (identify & name components)
The computer so far…
(identify & name components) ip
Data Memory
Instruction
Memory 1 4
mar

22. A couple of extra registers..
Memory Data Register
Instruction Register
Data Memory 1 4 1. 2
add ax,bx 2. 8 34
Instruction
Memory
Data
Energize ax
Energize bx
Select ALU “add" 2
Address 34
Line of code goes in…
Electrical bit signals come out

23. Moving data into Registers (ie from specified location)
mov ax , [1]
for example …
Instruction
Memory 1 2
mar 3 4 AX
mov ax , [1] BX
mov bx , [2] 5
mov bx , [2] 8 7 8 7 6 1

24. Moving data into Memory
For example …
mov [3] , ax
Instruction
Memory 1 2
mar 3 4
mov [0], bx AX
mov [3] , ax BX 5 7
mov [0] , bx 8 7 8 7 6 8 1

25. 8086 CPU family registers 8086 chip always used a 16-bit word
SAM simulates an 8-bit word
popular on most early microcomputers…
Typical 8086 registers (stores):
general purpose data: AX, BX, CX, DX
specific use e.g.
program counter (PC): instruction address in memory
stack pointer SP): address of the top of the “stack”

26. Data and Addressing General purpose register contents… Convention:
memory address that points to data
Convention:
data written as hexadecimal equivalent
e.g. 4A
memory location also has square brackets
e.g. [4A]

27. CPU Instructions Used to tell the CPU what to do…
MOV is for moving data around…
MOV AX, 4A – move “4A” into AX register
MOV AX, [4A] – move data contained in address 4A into AX register
Many other instructions; range of operations…
collectively known as an instruction set
each CPU family has its own unique codes

28. 8086 in practice Four 16-bit General Purpose registers
each gen register (e.g. AX) can be read/written to upper (AH) & lower (AL) byte
upper byte
lower byte AX AH AL BX BH BL CX CH CL DX DH DL

29. Another 8086 Instruction: ADD
Takes values from two registers
Adds them together
Deposits results back in one of the registers
Which one?
the register that appeared first
e.g. “MOV, AX, BX” puts result in AX

30. Fetch-Execute Cycle (Organization and Control)
1. Fetch instruction from memory
5. Write back results to registers
add ax , bx
ax <- ALU
4. Do any Memory Access
2. Decode the instruction and read any registers
(Data cache)
ALU <- ax ALU <- bx
None needed
3. Do any ALU operations (execute units)
ax + bx

31. Fetch-Exec : State 1 Instruction Fetch 3 3 1 8 7 1 9 add ax , bx AX BX1 4 3 2
add ax bx AX BX 3
add ax,bx 3 1 8 7 1 9

32. Fetch-Exec : State 2 Decode, Register Operations 3 3 1 8 7 3 1 1 9
add ax , bx 1 4 3 2
add ax bx AX BX 3
add ax,bx 3 1 8 7 3 1 1 9

33. Fetch-Exec : State 3 ALU Operation 3 8 7 3 1 4 1 9 add ax , bx AX BX 11 4 3 2
add ax bx AX BX 3
add ax,bx 8 1 7 3 4 1 9

34. Fetch-Exec : State 4 Memory Access 3 8 7 3 1 4 1 9 add ax , bx AX BX 11 4 3 2
add ax bx AX BX 3
add ax,bx 8 1 7 3 4 1 9

35. Fetch-Exec : State 5 Register Write 3 4 8 7 3 1 4 1 9 add ax , bx BX 11 4 3 2
add ax bx BX 3
add ax,bx 4 8 1 7 3 4 1 9

36. Fetch-Execute Cycle (Organization and Control)
1. Fetch instruction from memory
5. Write back results to registers
mov ax , [1]
Data into ax
4. Do any Memory Access
2. Decode the instruction and read any registers
Read memory at addr ‘1’
Read the ‘1’
3. Do any ALU operations (execute units)
Put ‘1’ into MAR

37. Fetch-Exec : State 1 Instruction Fetch 3 8 7 1 9 mov ax , [1] 1 2 3 41 4 3 2
mov ax 1
mov ax , [1] 3 8 7 1 9

38. Fetch-Exec : State 2 Decode, Register Operations 3 8 7 1 9
mov ax , [1] 1 4 3 2
mov ax 1
mov ax , [1] 3 8 7 1 9

39. Fetch-Exec : State 3 ALU Operation 3 8 7 1 9 mov ax , [1] 1 1 2 3 41 4 3 2
mov ax 1
mov ax , [1] 3 8 7 1 1 9

40. Fetch-Exec : State 4 Memory Access 3 8 8 7 1 9 mov ax , [1] 1 1 2 3 41 4 3 2
mov ax 1
mov ax , [1] 3 8 8 7 1 1 9

41. Fetch-Exec : State 5 Register Write 3 8 8 8 7 1 9 mov ax , [1] 1 1 2 31 4 3 2
mov ax 1
mov ax , [1] 3 8 8 8 7 1 1 9

42. 8088: Brains of the IBM PC

43. Inside the 8088 address bus address adder External buses gen registers
ALU

44. 1
Pentium (same family) 2
Fetch
Decode
ALU
Mem Ops
Reg Write 3 4 5

45. Intel Multi-core

46. Programming a CPU CPU programming code written as assembly language
each family has its own instruction set
Programming syntax depends on the
CPU/instructions
how they should be used
Intel 8086 assembly language used for CPUs that support PC platforms

47. Example 8086 Assembly Language
MOV AH,08
INT 21
MOV DL,AL
MOV AH,02
MOV AH,4C

48. So THAT’S how it all works
So THAT’S how it all works!  now you try it on SAM… Next week: a focus on writing programs and i/o